From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Lezcano Subject: Re: [PATCH v8 09/16] clockevents/drivers: Add STM32 Timer driver Date: Mon, 18 May 2015 15:10:08 +0200 Message-ID: <5559E4B0.70506@linaro.org> References: <1431158038-3813-1-git-send-email-mcoquelin.stm32@gmail.com> <1431158038-3813-10-git-send-email-mcoquelin.stm32@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <1431158038-3813-10-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-doc-owner@vger.kernel.org To: Maxime Coquelin , u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl, peter@hurleysoftware.com, andy.shevchenko@gmail.com, cw00.choi@samsung.com, Russell King , joe@perches.com, Vladimir Zapolskiy , lee.jones@linaro.org, Daniel Thompson Cc: Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kerne List-Id: linux-api@vger.kernel.org On 05/09/2015 09:53 AM, Maxime Coquelin wrote: > STM32 MCUs feature 16 and 32 bits general purpose timers with prescal= ers. > The drivers detects whether the time is 16 or 32 bits, and applies a > 1024 prescaler value if it is 16 bits. > > Reviewed-by: Linus Walleij > Tested-by: Chanwoo Choi > Signed-off-by: Maxime Coquelin > --- > drivers/clocksource/Kconfig | 8 ++ > drivers/clocksource/Makefile | 1 + > drivers/clocksource/timer-stm32.c | 184 +++++++++++++++++++++++++++= +++++++++++ > 3 files changed, 193 insertions(+) > create mode 100644 drivers/clocksource/timer-stm32.c > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfi= g > index bf9364c..2443520 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -106,6 +106,14 @@ config CLKSRC_EFM32 > Support to use the timers of EFM32 SoCs as clock source and cloc= k > event device. > > +config CLKSRC_STM32 > + bool "Clocksource for STM32 SoCs" if !ARCH_STM32 > + depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) Are the interactive bool and the 'COMPILE_TEST' necessary ? > + select CLKSRC_MMIO > + default ARCH_STM32 > + help > + Support to use the timers of STM32 SoCs as clock event device. > + > config ARM_ARCH_TIMER > bool > select CLKSRC_OF if OF > diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makef= ile > index d510c54..888a7df 100644 > --- a/drivers/clocksource/Makefile > +++ b/drivers/clocksource/Makefile > @@ -36,6 +36,7 @@ obj-$(CONFIG_ARCH_NSPIRE) +=3D zevio-timer.o > obj-$(CONFIG_ARCH_BCM_MOBILE) +=3D bcm_kona_timer.o > obj-$(CONFIG_CADENCE_TTC_TIMER) +=3D cadence_ttc_timer.o > obj-$(CONFIG_CLKSRC_EFM32) +=3D time-efm32.o > +obj-$(CONFIG_CLKSRC_STM32) +=3D timer-stm32.o > obj-$(CONFIG_CLKSRC_EXYNOS_MCT) +=3D exynos_mct.o > obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) +=3D samsung_pwm_timer.o > obj-$(CONFIG_FSL_FTM_TIMER) +=3D fsl_ftm_timer.o > diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/= timer-stm32.c > new file mode 100644 > index 0000000..fad2e2e > --- /dev/null > +++ b/drivers/clocksource/timer-stm32.c > @@ -0,0 +1,184 @@ > +/* > + * Copyright (C) Maxime Coquelin 2015 > + * Author: Maxime Coquelin > + * License terms: GNU General Public License (GPL), version 2 > + * > + * Inspired by time-efm32.c from Uwe Kleine-Koenig > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define TIM_CR1 0x00 > +#define TIM_DIER 0x0c > +#define TIM_SR 0x10 > +#define TIM_EGR 0x14 > +#define TIM_PSC 0x28 > +#define TIM_ARR 0x2c > + > +#define TIM_CR1_CEN BIT(0) > +#define TIM_CR1_OPM BIT(3) > +#define TIM_CR1_ARPE BIT(7) > + > +#define TIM_DIER_UIE BIT(0) > + > +#define TIM_SR_UIF BIT(0) > + > +#define TIM_EGR_UG BIT(0) > + > +struct stm32_clock_event_ddata { > + struct clock_event_device evtdev; > + unsigned periodic_top; > + void __iomem *base; > +}; > + > +static void stm32_clock_event_set_mode(enum clock_event_mode mode, > + struct clock_event_device *evtdev) > +{ > + struct stm32_clock_event_ddata *data =3D > + container_of(evtdev, struct stm32_clock_event_ddata, evtdev); > + void *base =3D data->base; > + > + switch (mode) { > + case CLOCK_EVT_MODE_PERIODIC: > + writel_relaxed(data->periodic_top, base + TIM_ARR); > + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); > + break; > + > + case CLOCK_EVT_MODE_ONESHOT: > + default: > + writel_relaxed(0, base + TIM_CR1); > + break; > + } > +} > + > +static int stm32_clock_event_set_next_event(unsigned long evt, > + struct clock_event_device *evtdev) > +{ > + struct stm32_clock_event_ddata *data =3D > + container_of(evtdev, struct stm32_clock_event_ddata, evtdev); > + > + writel_relaxed(evt, data->base + TIM_ARR); > + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, > + data->base + TIM_CR1); > + > + return 0; > +} > + > +static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) > +{ > + struct stm32_clock_event_ddata *data =3D dev_id; > + > + writel_relaxed(0, data->base + TIM_SR); > + > + data->evtdev.event_handler(&data->evtdev); > + > + return IRQ_HANDLED; > +} > + > +static struct stm32_clock_event_ddata clock_event_ddata =3D { > + .evtdev =3D { > + .name =3D "stm32 clockevent", > + .features =3D CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, > + .set_mode =3D stm32_clock_event_set_mode, > + .set_next_event =3D stm32_clock_event_set_next_event, > + .rating =3D 200, > + }, > +}; > + > +static void __init stm32_clockevent_init(struct device_node *np) > +{ > + struct stm32_clock_event_ddata *data =3D &clock_event_ddata; > + struct clk *clk; > + struct reset_control *rstc; > + unsigned long rate, max_delta; > + int irq, ret, bits, prescaler =3D 1; > + > + clk =3D of_clk_get(np, 0); > + if (IS_ERR(clk)) { > + ret =3D PTR_ERR(clk); > + pr_err("failed to get clock for clockevent (%d)\n", ret); > + goto err_clk_get; > + } > + > + ret =3D clk_prepare_enable(clk); > + if (ret) { > + pr_err("failed to enable timer clock for clockevent (%d)\n", > + ret); > + goto err_clk_enable; > + } > + > + rate =3D clk_get_rate(clk); > + > + rstc =3D of_reset_control_get(np, NULL); > + if (!IS_ERR(rstc)) { > + reset_control_assert(rstc); > + reset_control_deassert(rstc); > + } > + > + data->base =3D of_iomap(np, 0); > + if (!data->base) { > + pr_err("failed to map registers for clockevent\n"); > + goto err_iomap; > + } > + > + irq =3D irq_of_parse_and_map(np, 0); > + if (!irq) { > + pr_err("%s: failed to get irq.\n", np->full_name); > + goto err_get_irq; > + } > + > + /* Detect whether the timer is 16 or 32 bits */ > + writel_relaxed(~0UL, data->base + TIM_ARR); > + max_delta =3D readl_relaxed(data->base + TIM_ARR); > + if (max_delta =3D=3D ~0UL) { > + prescaler =3D 1; > + bits =3D 32; > + } else { > + prescaler =3D 1024; > + bits =3D 16; > + } > + writel_relaxed(0, data->base + TIM_ARR); > + > + writel_relaxed(prescaler - 1, data->base + TIM_PSC); > + writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); > + writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); > + writel_relaxed(0, data->base + TIM_SR); > + > + data->periodic_top =3D DIV_ROUND_CLOSEST(rate, prescaler * HZ); > + > + clockevents_config_and_register(&data->evtdev, > + DIV_ROUND_CLOSEST(rate, prescaler), > + 0x1, max_delta); > + > + ret =3D request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, > + "stm32 clockevent", data); > + if (ret) { > + pr_err("%s: failed to request irq.\n", np->full_name); > + goto err_get_irq; > + } > + > + pr_info("%s: STM32 clockevent driver initialized (%d bits)\n", > + np->full_name, bits); > + > + return; > + > +err_get_irq: > + iounmap(data->base); > +err_iomap: > + clk_disable_unprepare(clk); > +err_clk_enable: > + clk_put(clk); > +err_clk_get: > + return; > +} > + > +CLOCKSOURCE_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_ini= t); > --=20 Linaro.org =E2=94=82 Open source software fo= r ARM SoCs =46ollow Linaro: Facebook | Twitter | Blog