From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mathieu Desnoyers Subject: Re: [RFC PATCH 0/2] x86: Fix missing core serialization on migration Date: Tue, 14 Nov 2017 16:49:15 +0000 (UTC) Message-ID: <798843926.14994.1510678155257.JavaMail.zimbra@efficios.com> References: <20171110211249.10742-1-mathieu.desnoyers@efficios.com> <885227610.13045.1510351034488.JavaMail.zimbra@efficios.com> <617343212.13932.1510592207202.JavaMail.zimbra@efficios.com> <4d47fbb8-8f99-19d3-a9cf-66841aeffac3@scylladb.com> <4431530.14831.1510672632887.JavaMail.zimbra@efficios.com> <20171114160541.GC3165@worktop.lehotels.local> <20171114160842.GH3857@worktop> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20171114160842.GH3857@worktop> Sender: linux-api-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Peter Zijlstra Cc: Avi Kivity , Linus Torvalds , Andy Lutomirski , linux-kernel , linux-api , "Paul E. McKenney" , Boqun Feng , Andrew Hunter , maged michael , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Dave Watson , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andrea Parri , "Russell King, ARM Linux" , Greg Hackmann List-Id: linux-api@vger.kernel.org ----- On Nov 14, 2017, at 11:08 AM, Peter Zijlstra peterz-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org wrote: > On Tue, Nov 14, 2017 at 05:05:41PM +0100, Peter Zijlstra wrote: >> On Tue, Nov 14, 2017 at 03:17:12PM +0000, Mathieu Desnoyers wrote: >> > I've tried to create a small single-threaded self-modifying loop in >> > user-space to trigger a trace cache or speculative execution quirk, >> > but I have not succeeded yet. I suspect that I would need to know >> > more about the internals of the processor architecture to create the >> > right stalls that would allow speculative execution to move further >> > ahead, and trigger an incoherent execution flow. Ideas on how to >> > trigger this would be welcome. >> >> I thought the whole problem was per definition multi-threaded. >> >> Single-threaded stuff can't get out of sync with itself; you'll always >> observe your own stores. > > And even if you could, you can always execute a local serializing > instruction like CPUID to force things. What I'm trying to reproduce is something that breaks in single-threaded case if I explicitly leave out the CPUID core serializing instruction when doing code modification on upcoming code, in a loop. AFAIU, Intel requires a core serializing instruction to be issued even in single-threaded scenarios between code update and execution, to ensure that speculative execution does not observe incoherent code. Now the question we all have for Intel is: is this requirement too strong, or required by reality ? Thanks, Mathieu > >> And ISTR the JIT scenario being something like the JIT overwriting >> previously executed but supposedly no longer used code. And in this >> scenario you'd want to guarantee all CPUs observe the new code before >> jumping into it. >> >> The current approach is using mprotect(), except that on a number of >> platforms the TLB invalidate from that is not guaranteed to be strong >> enough to sync for code changes. >> >> On x86 the mprotect() should work just fine, since we broadcast IPIs for >> the TLB invalidate and the IRET from those will get the things synced up >> again (if nothing else; very likely we'll have done a MOV-CR3 which will >> of course also have sufficient syncness on it). >> >> But PowerPC, s390, ARM et al that do TLB invalidates without interrupts >> and don't guarantee their TLB invalidate sync against execution units >> are left broken by this scheme. -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com