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From: Alexander Shishkin <alexander.shishkin@linux.intel.com>
To: Al Grant <Al.Grant@arm.com>,
	Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Chunyan Zhang <zhang.chunyan@linaro.org>,
	"robh@kernel.org" <robh@kernel.org>,
	Mark Brown <broonie@kernel.org>,
	Pratik Patel <pratikp@codeaurora.org>,
	Nicolas GUION <nicolas.guion@st.com>, Jon Corbet <corbet@lwn.net>,
	Mark Rutland <Mark.Rutland@arm.com>,
	Mike Leach <Mike.Leach@arm.com>, "Jeremiassen, Tor" <tor@ti.com>,
	Lyra Zhang <zhang.lyra@gmail.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-api@vger.kernel.org" <linux-api@vger.kernel.org>,
	"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>
Subject: RE: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs
Date: Fri, 12 Feb 2016 17:54:41 +0200	[thread overview]
Message-ID: <87twld3ovy.fsf@ashishki-desk.ger.corp.intel.com> (raw)
In-Reply-To: <AM4PR08MB0785EAA2B628765D7EA3FDA086D50@AM4PR08MB0785.eurprd08.prod.outlook.com>

Al Grant <Al.Grant@arm.com> writes:

>> Mike did write "master IDs are hardwired to individual cores and core security
>> states", which make assignment for one platform very static.
>> On the flip side those will change from one system to another.
>
> It depends on your perspective.  From the perspective of a userspace
> process not pinned to a core, the master id will appear to vary
> dynamically and unpredictably as the thread migrates from one
> core to another.  (That's actually useful if the decoder wants to know
> where the thread is running at any given point, as it can find that out
> for free, without the need to track migration events.)
>
> On the other hand if you are pinned (e.g. you're the kernel on a
> particular core, or you're a per-core worker thread in some thread
> pooling system) then you have a fixed master id, and then you can
> have one instance per core all using the same range of channel
> numbers, with the master id indicating the core - this saves on
> channel space compared to having to give each core its own
> range of channel space.

What I understood from Mike's explanation is that basically nothing is
fixed from the software perspective (talking about Coresight STM). One
doesn't know the master id with which one's data will be tagged,
regardless of whether one is cpu-affine or not, because:

 * even per-core master IDs will be highly implementation dependent and
   therefore not knowable by the kernel and subsequently userspace,
 * master IDs may change based on other conditions (besides security
   states), so even if we knew per-core master IDs for sure, it wouldn't
   give us the complete picture.

So even though from the HW perspective master IDs may be "hardwired" to
hardware states, the hardware states themselves are dynamic, so from the
SW perspective these master IDs are not static or hardwired at all.

If the same mmio write done by software would always result in the exact
same master ID tagged to it, that would be more like "static" to me.

Regards,

  parent reply	other threads:[~2016-02-12 15:54 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-03  8:15 [PATCH V2 0/6] Introduce CoreSight STM support Chunyan Zhang
2016-02-03  8:15 ` [PATCH V2 1/6] stm class: Add ioctl get_options interface Chunyan Zhang
     [not found]   ` <1454487337-30184-2-git-send-email-zhang.chunyan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-02-05 12:55     ` Alexander Shishkin
2016-02-03  8:15 ` [PATCH V2 2/6] stm class: adds a loop to extract the first valid STM device name Chunyan Zhang
2016-02-03 10:05   ` kbuild test robot
2016-02-03 10:05   ` [PATCH] stm class: fix semicolon.cocci warnings kbuild test robot
2016-02-04  8:56   ` [PATCH V2 2/6] stm class: adds a loop to extract the first valid STM device name Chunyan Zhang
2016-02-04 17:30     ` Alexander Shishkin
2016-02-05  3:18       ` Chunyan Zhang
2016-02-03  8:15 ` [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Chunyan Zhang
2016-02-05 12:52   ` Alexander Shishkin
2016-02-05 16:31     ` Mike Leach
     [not found]       ` <DB3PR08MB0041B8843C61FCEB049B2BB58CD20-aD6Q2MAZY6WInpB6pqslIikoKrxaZxrJvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-02-08 10:52         ` Alexander Shishkin
2016-02-05 18:08     ` Mathieu Poirier
2016-02-08 13:26       ` Alexander Shishkin
2016-02-08 17:05         ` Mathieu Poirier
     [not found]           ` <CANLsYkw=mG+ch8QzxmbwWs9o+mndVNo1MuqXcrPrNJYj_SQcHQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-02-08 17:44             ` Al Grant
2016-02-09 17:06               ` Mathieu Poirier
2016-02-12 15:54               ` Alexander Shishkin [this message]
2016-02-12 16:27           ` Alexander Shishkin
2016-02-12 20:33             ` Mathieu Poirier
2016-02-22 18:01               ` Mathieu Poirier
2016-02-03  8:15 ` [PATCH V2 4/6] Documentations: Add explanations of the case for non-configurable masters Chunyan Zhang
2016-02-03  8:15 ` [PATCH V2 5/6] coresight-stm: Bindings for System Trace Macrocell Chunyan Zhang
2016-02-03  8:15 ` [PATCH V2 6/6] coresight-stm: adding driver for CoreSight STM component Chunyan Zhang
2016-02-05 13:06   ` Alexander Shishkin
     [not found]     ` <87h9hn5msz.fsf-qxRn5AmX6ZD9BXuAQUXR0fooFf0ArEBIu+b9c/7xato@public.gmane.org>
2016-02-05 14:30       ` Arnd Bergmann

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