From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alan Tull Subject: Re: [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device Date: Mon, 4 Dec 2017 13:46:59 -0600 Message-ID: References: <1511764948-20972-1-git-send-email-hao.wu@intel.com> <1511764948-20972-9-git-send-email-hao.wu@intel.com> <20171128031519.GA25705@hao-dev> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <20171128031519.GA25705@hao-dev> Sender: linux-api-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Wu Hao Cc: David Laight , "mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "linux-fpga-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-api-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "luwei.kang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org" , "yi.z.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org" , Tim Whisonant , Enno Luebbers , Shiva Rao , Christopher Rauer , Xiao Guangrong List-Id: linux-api@vger.kernel.org On Mon, Nov 27, 2017 at 9:15 PM, Wu Hao wrote: > On Mon, Nov 27, 2017 at 10:28:04AM +0000, David Laight wrote: >> From: Wu Hao >> > Sent: 27 November 2017 06:42 >> > From: Zhang Yi >> > >> > The Intel FPGA device appears as a PCIe device on the system. This patch >> > implements the basic framework of the driver for Intel PCIe device which >> > is located between CPU and Accelerated Function Units (AFUs), and has >> > the Device Feature List (DFL) implemented in its MMIO space. >> >> This ought to have a better name than 'Intel FPGA'. >> An fpga can be used for all sorts of things, this looks like >> a very specific architecture using a common VHDL environment to >> allow certain types of user VHDL be accessed over PCIe. > > Hi David > > This patch adds a pcie device driver for Intel FPGA devices which implements > the DFL, e.g Intel Server Platform with In-package FPGA and Intel FPGA PCIe > Acceleration Cards. They are pcie devices, and all have DFL implemented in > the MMIO space, so we would like to use one kernel driver to handle them. > > With this full patchset, it just provides user the interfaces to configure > and access the FPGA accelerators on Intel DFL based FPGA devices. For sure, > users can develop and build their own logics via tools provided by Intel, > program them to accelerators on these Intel FPGA devices, and access them > for their workloads. I don't see anything Intel specific here. This could all be named dfl-* Alan > > Thanks > Hao