From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alan Tull Subject: Re: [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth Date: Thu, 28 Mar 2019 13:50:11 -0500 Message-ID: References: <1553483264-5379-1-git-send-email-hao.wu@intel.com> <1553483264-5379-3-git-send-email-hao.wu@intel.com> <20190326002852.GA2901@hao-dev> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <20190326002852.GA2901@hao-dev> Sender: linux-kernel-owner@vger.kernel.org To: Wu Hao Cc: Moritz Fischer , linux-fpga@vger.kernel.org, linux-kernel , linux-api@vger.kernel.org, Xu Yilun List-Id: linux-api@vger.kernel.org On Mon, Mar 25, 2019 at 7:44 PM Wu Hao wrote: > > On Mon, Mar 25, 2019 at 12:50:40PM -0500, Alan Tull wrote: > > On Sun, Mar 24, 2019 at 10:23 PM Wu Hao wrote: > > > > Hi Hao, > > > > Looks good, one question below. > > > > > > > > Current driver checks if input bitstream file size is aligned or > > > not per PR data width (default 32bits). It requires one additional > > > step for end user when they generate the bitstream file, padding > > > extra zeros to bitstream file to align its size per PR data width, > > > but they don't have to as hardware will drop extra padding bytes > > > automatically. > > > > > > In order to simplify the user steps, this patch aligns PR buffer > > > size per PR data width in driver, to allow user to pass unaligned > > > size bitstream files to driver. > > > > > > Signed-off-by: Xu Yilun > > > Signed-off-by: Wu Hao Acked-by: Alan Tull Thanks, Alan