Re: [PATCH v3 2/3] RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto

[Conor Dooley <conor@kernel.org>]

On 24/11/2022 17:12, Samuel Ortiz wrote:
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> On Thu, Nov 24, 2022 at 11:55:01AM +0000, Conor Dooley wrote:
>> On Thu, Nov 24, 2022 at 11:47:30AM +0100, Samuel Ortiz wrote:
>>
>>> Patch #1 is definitely needed regardless of which interface we pick for
>>> exposing the ISA strings to userspace.
>>
>> I took another look at #1, and I feel more confused about what
>> constitutes canonical order than I did before! If you know better than
>> I, and you probably do since you're interested in these 6 month old
>> patches, some insight would be appreciated!
> 
> Assuming we don't go with hwcap, I dont think the order of the
> riscv_isa_ext_id enum matters that much?

The chief put it in canonical order so that's good enough for me!

> 
> iiuc we're building the cpuinfo string from the riscv_isa_ext_data
> array, and I think the current code is incorrect:
> 
> static struct riscv_isa_ext_data isa_ext_arr[] = {
>     __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
>     __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
>     __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
>     __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
>     __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
>     __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
>     __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
> };
> 
> zicbom and zihintpause should come before supervisor level extensions.
> I'm going to send a patch for that.

idk, Palmer explicitly re-ordered this:
https://lore.kernel.org/linux-riscv/20220920204518.10988-1-palmer@rivosinc.com/

By my reading of the isa manual, what Palmer did is correct as
those are not "Additional Standard Extensions". /shrug

> 
> And the Zb/Zk ones should come after the Zi ones, and before the
> supervisor level ones (The I category comes before the B or the K one).

This I agree with though.