* [patch v26 2/4] drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master driver
From: Oleksandr Shamray @ 2018-06-15 16:45 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, vadimp, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray
In-Reply-To: <1529081123-30873-1-git-send-email-oleksandrs@mellanox.com>
Driver adds support of Aspeed 2500/2400 series SOC JTAG master controller.
Driver implements the following jtag ops:
- freq_get;
- freq_set;
- status_get;
- idle;
- xfer;
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
Acked-by: Joel Stanley <joel@jms.id.au>
---
v24->v25
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- reduced debug printouts
v23->v24
v22->v23
v21->v22
Comments pointed by Andy Shevchenko <andy.shevchenko@gmail.com>
- rearrange ASPEED register defines
- simplified JTAG divider calculation formula
- change delay function in bit-bang operation
- add helper functions for TAP states switching
- remove unnecessary comments
- remove redundant debug messages
- make dines for repetative register bit sets
- fixed indentation
- change checks from negative to positive
- add error check for clk_prepare_enable
- rework driver alloc/register to devm_ variant
- Increasing line length up to 85 in order to improve readability
v20->v21
v19->v20
Notifications from kbuild test robot <lkp@intel.com>
- add static declaration to 'aspeed_jtag_init' and
'aspeed_jtag_deinit' functions
v18->v19
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- Add reset_control on Jtag init/deinit
v14->v15
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- Add ARCH_ASPEED || COMPILE_TEST to Kconfig
- remove unused offset variable
- remove "aspeed_jtag" from dev_err and dev_dbg messages
- change clk_prepare_enable initialisation order
v13->v14
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change style of head block comment from /**/ to //
v12->v13
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change jtag-aspeed.c licence type to
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
and reorder line with license- add reset descriptions in bndings file
in description
Comments pointed by Kun Yi <kunyi@google.com>
- Changed capability check for aspeed,ast2400-jtag/ast200-jtag
v11->v12
Comments pointed by Chip Bilbrey <chip@bilbrey.org>
- Remove access mode from xfer and idle transactions
- Add new ioctl JTAG_SIOCMODE for set hw mode
v10->v11
v9->v10
V8->v9
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- add *data parameter to xfer function prototype
v7->v8
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- aspeed_jtag_init replace goto to return;
- change input variables type from __u32 to u32
in functios freq_get, freq_set, status_get
- change sm_ variables type from char to u8
- in jatg_init add disable clocks on error case
- remove release_mem_region on error case
- remove devm_free_irq on jtag_deinit
- Fix misspelling Disabe/Disable
- Change compatible string to ast2400 and ast2000
v6->v7
Notifications from kbuild test robot <lkp@intel.com>
- Add include <linux/types.h> to jtag-asapeed.c
v5->v6
v4->v5
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- Added HAS_IOMEM dependence in Kconfig to avoid
"undefined reference to `devm_ioremap_resource'" error,
because in some arch this not supported
v3->v4
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- change transaction pointer tdio type to __u64
- change internal status type from enum to __u32
v2->v3
v1->v2
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- change license type from GPLv2/BSD to GPLv2
Comments pointed by Neil Armstrong <narmstrong@baylibre.com>
- Add clk_prepare_enable/clk_disable_unprepare in clock init/deinit
- Change .compatible to soc-specific compatible names
aspeed,aspeed4000-jtag/aspeed5000-jtag
- Added dt-bindings
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- Reorder functions and removed the forward declarations
- Add static const qualifier to state machine states transitions
- Change .compatible to soc-specific compatible names
aspeed,aspeed4000-jtag/aspeed5000-jtag
- Add dt-bindings
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Change module name jtag-aspeed in description in Kconfig
Comments pointed by kbuild test robot <lkp@intel.com>
- Remove invalid include <asm/mach-types.h>
- add resource_size instead of calculation
---
drivers/jtag/Kconfig | 14 +
drivers/jtag/Makefile | 1 +
drivers/jtag/jtag-aspeed.c | 756 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 771 insertions(+), 0 deletions(-)
create mode 100644 drivers/jtag/jtag-aspeed.c
diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig
index 47771fc..0cc163f 100644
--- a/drivers/jtag/Kconfig
+++ b/drivers/jtag/Kconfig
@@ -15,3 +15,17 @@ menuconfig JTAG
To compile this driver as a module, choose M here: the module will
be called jtag.
+
+menuconfig JTAG_ASPEED
+ tristate "Aspeed SoC JTAG controller support"
+ depends on JTAG && HAS_IOMEM
+ depends on ARCH_ASPEED || COMPILE_TEST
+ help
+ This provides a support for Aspeed JTAG device, equipped on
+ Aspeed SoC 24xx and 25xx families. Drivers allows programming
+ of hardware devices, connected to SoC through the JTAG interface.
+
+ If you want this support, you should say Y here.
+
+ To compile this driver as a module, choose M here: the module will
+ be called jtag-aspeed.
diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
index af37493..04a855e 100644
--- a/drivers/jtag/Makefile
+++ b/drivers/jtag/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_JTAG) += jtag.o
+obj-$(CONFIG_JTAG_ASPEED) += jtag-aspeed.o
diff --git a/drivers/jtag/jtag-aspeed.c b/drivers/jtag/jtag-aspeed.c
new file mode 100644
index 0000000..15ae188
--- /dev/null
+++ b/drivers/jtag/jtag-aspeed.c
@@ -0,0 +1,756 @@
+// SPDX-License-Identifier: GPL-2.0
+// drivers/jtag/aspeed-jtag.c
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/jtag.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <uapi/linux/jtag.h>
+
+#define ASPEED_JTAG_DATA 0x00
+#define ASPEED_JTAG_INST 0x04
+#define ASPEED_JTAG_CTRL 0x08
+#define ASPEED_JTAG_ISR 0x0C
+#define ASPEED_JTAG_SW 0x10
+#define ASPEED_JTAG_TCK 0x14
+#define ASPEED_JTAG_EC 0x18
+
+#define ASPEED_JTAG_DATA_MSB 0x01
+#define ASPEED_JTAG_DATA_CHUNK_SIZE 0x20
+
+/* ASPEED_JTAG_CTRL: Engine Control */
+#define ASPEED_JTAG_CTL_ENG_EN BIT(31)
+#define ASPEED_JTAG_CTL_ENG_OUT_EN BIT(30)
+#define ASPEED_JTAG_CTL_FORCE_TMS BIT(29)
+#define ASPEED_JTAG_CTL_INST_LEN(x) ((x) << 20)
+#define ASPEED_JTAG_CTL_LASPEED_INST BIT(17)
+#define ASPEED_JTAG_CTL_INST_EN BIT(16)
+#define ASPEED_JTAG_CTL_DR_UPDATE BIT(10)
+#define ASPEED_JTAG_CTL_DATA_LEN(x) ((x) << 4)
+#define ASPEED_JTAG_CTL_LASPEED_DATA BIT(1)
+#define ASPEED_JTAG_CTL_DATA_EN BIT(0)
+
+/* ASPEED_JTAG_ISR : Interrupt status and enable */
+#define ASPEED_JTAG_ISR_INST_PAUSE BIT(19)
+#define ASPEED_JTAG_ISR_INST_COMPLETE BIT(18)
+#define ASPEED_JTAG_ISR_DATA_PAUSE BIT(17)
+#define ASPEED_JTAG_ISR_DATA_COMPLETE BIT(16)
+#define ASPEED_JTAG_ISR_INST_PAUSE_EN BIT(3)
+#define ASPEED_JTAG_ISR_INST_COMPLETE_EN BIT(2)
+#define ASPEED_JTAG_ISR_DATA_PAUSE_EN BIT(1)
+#define ASPEED_JTAG_ISR_DATA_COMPLETE_EN BIT(0)
+#define ASPEED_JTAG_ISR_INT_EN_MASK GENMASK(3, 0)
+#define ASPEED_JTAG_ISR_INT_MASK GENMASK(19, 16)
+
+/* ASPEED_JTAG_SW : Software Mode and Status */
+#define ASPEED_JTAG_SW_MODE_EN BIT(19)
+#define ASPEED_JTAG_SW_MODE_TCK BIT(18)
+#define ASPEED_JTAG_SW_MODE_TMS BIT(17)
+#define ASPEED_JTAG_SW_MODE_TDIO BIT(16)
+
+/* ASPEED_JTAG_TCK : TCK Control */
+#define ASPEED_JTAG_TCK_DIVISOR_MASK GENMASK(10, 0)
+#define ASPEED_JTAG_TCK_GET_DIV(x) ((x) & ASPEED_JTAG_TCK_DIVISOR_MASK)
+
+/* ASPEED_JTAG_EC : Controller set for go to IDLE */
+#define ASPEED_JTAG_EC_GO_IDLE BIT(0)
+
+#define ASPEED_JTAG_IOUT_LEN(len) \
+ (ASPEED_JTAG_CTL_ENG_EN | \
+ ASPEED_JTAG_CTL_ENG_OUT_EN | \
+ ASPEED_JTAG_CTL_INST_LEN(len))
+
+#define ASPEED_JTAG_DOUT_LEN(len) \
+ (ASPEED_JTAG_CTL_ENG_EN | \
+ ASPEED_JTAG_CTL_ENG_OUT_EN | \
+ ASPEED_JTAG_CTL_DATA_LEN(len))
+
+#define ASPEED_JTAG_SW_TDIO (ASPEED_JTAG_SW_MODE_EN | ASPEED_JTAG_SW_MODE_TDIO)
+
+#define ASPEED_JTAG_GET_TDI(direction, byte) \
+ ((direction == JTAG_READ_XFER) ? UINT_MAX : byte)
+
+#define ASPEED_JTAG_TCK_WAIT 10
+#define ASPEED_JTAG_RESET_CNTR 10
+
+#define ASPEED_JTAG_NAME "jtag-aspeed"
+
+struct aspeed_jtag {
+ void __iomem *reg_base;
+ struct device *dev;
+ struct clk *pclk;
+ enum jtag_endstate status;
+ int irq;
+ struct reset_control *rst;
+ u32 flag;
+ wait_queue_head_t jtag_wq;
+ u32 mode;
+};
+
+static char *end_status_str[] = {"idle", "ir pause", "drpause"};
+
+static u32 aspeed_jtag_read(struct aspeed_jtag *aspeed_jtag, u32 reg)
+{
+ return readl(aspeed_jtag->reg_base + reg);
+}
+
+static void
+aspeed_jtag_write(struct aspeed_jtag *aspeed_jtag, u32 val, u32 reg)
+{
+ writel(val, aspeed_jtag->reg_base + reg);
+}
+
+static int aspeed_jtag_freq_set(struct jtag *jtag, u32 freq)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+ unsigned long apb_frq;
+ u32 tck_val;
+ u16 div;
+
+ apb_frq = clk_get_rate(aspeed_jtag->pclk);
+ if (!apb_frq)
+ return -ENOTSUPP;
+
+ div = (apb_frq - 1) / freq;
+ tck_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK);
+ aspeed_jtag_write(aspeed_jtag,
+ (tck_val & ASPEED_JTAG_TCK_DIVISOR_MASK) | div,
+ ASPEED_JTAG_TCK);
+ return 0;
+}
+
+static int aspeed_jtag_freq_get(struct jtag *jtag, u32 *frq)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+ u32 pclk;
+ u32 tck;
+
+ pclk = clk_get_rate(aspeed_jtag->pclk);
+ tck = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK);
+ *frq = pclk / (ASPEED_JTAG_TCK_GET_DIV(tck) + 1);
+
+ return 0;
+}
+
+static int aspeed_jtag_mode_set(struct jtag *jtag, u32 mode)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ aspeed_jtag->mode = mode;
+ return 0;
+}
+
+static void aspeed_jtag_sw_delay(struct aspeed_jtag *aspeed_jtag, int cnt)
+{
+ int i;
+
+ for (i = 0; i < cnt; i++)
+ aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_SW);
+}
+
+static char aspeed_jtag_tck_cycle(struct aspeed_jtag *aspeed_jtag,
+ u8 tms, u8 tdi)
+{
+ char tdo = 0;
+
+ /* TCK = 0 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+
+ ndelay(ASPEED_JTAG_TCK_WAIT);
+ aspeed_jtag_sw_delay(aspeed_jtag, ASPEED_JTAG_TCK_WAIT);
+
+ /* TCK = 1 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TCK |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+
+ if (aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_SW) &
+ ASPEED_JTAG_SW_MODE_TDIO)
+ tdo = 1;
+
+ aspeed_jtag_sw_delay(aspeed_jtag, ASPEED_JTAG_TCK_WAIT);
+
+ /* TCK = 0 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+ return tdo;
+}
+
+static void aspeed_jtag_wait_instruction_pause(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq,
+ aspeed_jtag->flag & ASPEED_JTAG_ISR_INST_PAUSE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_INST_PAUSE;
+}
+
+static void
+aspeed_jtag_wait_instruction_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq,
+ aspeed_jtag->flag & ASPEED_JTAG_ISR_INST_COMPLETE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_INST_COMPLETE;
+}
+
+static void
+aspeed_jtag_wait_data_pause_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq,
+ aspeed_jtag->flag & ASPEED_JTAG_ISR_DATA_PAUSE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_DATA_PAUSE;
+}
+
+static void aspeed_jtag_wait_data_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq,
+ aspeed_jtag->flag & ASPEED_JTAG_ISR_DATA_COMPLETE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_DATA_COMPLETE;
+}
+
+static void aspeed_jtag_sm_cycle(struct aspeed_jtag *aspeed_jtag,
+ const u8 *tms, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, tms[i], 0);
+}
+
+static void aspeed_jtag_run_idle(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ static const u8 sm_idle_irpause[] = {1, 1, 0, 1, 0};
+ static const u8 sm_idle_drpause[] = {1, 0, 1, 0};
+
+ switch (runtest->endstate) {
+ case JTAG_STATE_PAUSEIR:
+ /* ->DRSCan->IRSCan->IRCap->IRExit1->PauseIR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_idle_irpause,
+ sizeof(sm_idle_irpause));
+ aspeed_jtag->status = JTAG_STATE_PAUSEIR;
+ break;
+ case JTAG_STATE_PAUSEDR:
+ /* ->DRSCan->DRCap->DRExit1->PauseDR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_idle_drpause,
+ sizeof(sm_idle_drpause));
+
+ aspeed_jtag->status = JTAG_STATE_PAUSEDR;
+ break;
+ case JTAG_STATE_IDLE:
+ /* IDLE */
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ break;
+ default:
+ break;
+ }
+}
+
+static void aspeed_jtag_run_pause(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ static const u8 sm_pause_irpause[] = {1, 1, 1, 1, 0, 1, 0};
+ static const u8 sm_pause_drpause[] = {1, 1, 1, 0, 1, 0};
+ static const u8 sm_pause_idle[] = {1, 1, 0};
+
+ /* From IR/DR Pa.use */
+ switch (runtest->endstate) {
+ case JTAG_STATE_PAUSEIR:
+ /*
+ * to Exit2 IR/DR->Updt IR/DR->DRSCan->IRSCan->IRCap->
+ * IRExit1->PauseIR
+ */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_irpause,
+ sizeof(sm_pause_irpause));
+
+ aspeed_jtag->status = JTAG_STATE_PAUSEIR;
+ break;
+ case JTAG_STATE_PAUSEDR:
+ /*
+ * to Exit2 IR/DR->Updt IR/DR->DRSCan->DRCap->
+ * DRExit1->PauseDR
+ */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_drpause,
+ sizeof(sm_pause_drpause));
+ aspeed_jtag->status = JTAG_STATE_PAUSEDR;
+ break;
+ case JTAG_STATE_IDLE:
+ /* to Exit2 IR/DR->Updt IR/DR->IDLE */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_idle,
+ sizeof(sm_pause_idle));
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ break;
+ default:
+ break;
+ }
+}
+
+static void aspeed_jtag_run_test_idle_sw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ int i;
+
+ /* SW mode from idle/pause-> to pause/idle */
+ if (runtest->reset) {
+ for (i = 0; i < ASPEED_JTAG_RESET_CNTR; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, 1, 0);
+ }
+
+ switch (aspeed_jtag->status) {
+ case JTAG_STATE_IDLE:
+ aspeed_jtag_run_idle(aspeed_jtag, runtest);
+ break;
+
+ case JTAG_STATE_PAUSEIR:
+ /* Fall-through */
+ case JTAG_STATE_PAUSEDR:
+ aspeed_jtag_run_pause(aspeed_jtag, runtest);
+ break;
+
+ default:
+ dev_err(aspeed_jtag->dev, "aspeed_jtag_run_test_idle error\n");
+ break;
+ }
+
+ /* Stay on IDLE for at least TCK cycle */
+ for (i = 0; i < runtest->tck; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+}
+
+static int aspeed_jtag_idle(struct jtag *jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ dev_dbg(aspeed_jtag->dev, "runtest, state:%s\n",
+ end_status_str[runtest->endstate]);
+
+ if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) {
+ aspeed_jtag_run_test_idle_sw(aspeed_jtag, runtest);
+ return 0;
+ }
+
+ /* Disable sw mode */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW);
+ /* x TMS high + 1 TMS low */
+ if (runtest->reset)
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_CTL_ENG_EN |
+ ASPEED_JTAG_CTL_ENG_OUT_EN |
+ ASPEED_JTAG_CTL_FORCE_TMS, ASPEED_JTAG_CTRL);
+ else
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_EC_GO_IDLE,
+ ASPEED_JTAG_EC);
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_TDIO, ASPEED_JTAG_SW);
+
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ return 0;
+}
+
+static void aspeed_jtag_xfer_sw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_xfer *xfer, u32 *data)
+{
+ static const u8 sm_update_shiftir[] = { 1, 1, 0, 0 };
+ static const u8 sm_update_shiftdr[] = { 1, 0, 0 };
+ static const u8 sm_pause_idle[] = { 1, 1, 0 };
+ static const u8 sm_pause_update[] = { 1, 1 };
+ unsigned long remain_xfer = xfer->length;
+ unsigned long shift_bits = 0;
+ unsigned long index = 0;
+ unsigned long tdi;
+ char tdo;
+
+ if (aspeed_jtag->status != JTAG_STATE_IDLE) {
+ /*IR/DR Pause->Exit2 IR / DR->Update IR /DR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_update,
+ sizeof(sm_pause_update));
+ }
+
+ if (xfer->type == JTAG_SIR_XFER)
+ /* ->IRSCan->CapIR->ShiftIR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_update_shiftir,
+ sizeof(sm_update_shiftir));
+ else
+ /* ->DRScan->DRCap->DRShift */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_update_shiftdr,
+ sizeof(sm_update_shiftdr));
+
+ tdi = ASPEED_JTAG_GET_TDI(xfer->direction, data[index]);
+
+ while (remain_xfer > 1) {
+ tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 0,
+ tdi & ASPEED_JTAG_DATA_MSB);
+ data[index] |= tdo << (shift_bits %
+ ASPEED_JTAG_DATA_CHUNK_SIZE);
+
+ tdi >>= 1;
+ shift_bits++;
+ remain_xfer--;
+
+ if (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE == 0) {
+ tdo = 0;
+ index++;
+
+ tdi = ASPEED_JTAG_GET_TDI(xfer->direction, data[index]);
+ }
+ }
+
+ tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 1, tdi & ASPEED_JTAG_DATA_MSB);
+ data[index] |= tdo << (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE);
+
+ /* DIPause/DRPause */
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+
+ if (xfer->endstate == JTAG_STATE_IDLE) {
+ /* ->DRExit2->DRUpdate->IDLE */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_idle,
+ sizeof(sm_pause_idle));
+ }
+}
+
+static void aspeed_jtag_xfer_push_data(struct aspeed_jtag *aspeed_jtag,
+ enum jtag_xfer_type type, u32 bits_len)
+{
+ if (type == JTAG_SIR_XFER) {
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_IOUT_LEN(bits_len),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len) |
+ ASPEED_JTAG_CTL_INST_EN, ASPEED_JTAG_CTRL);
+ } else {
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len) |
+ ASPEED_JTAG_CTL_DATA_EN, ASPEED_JTAG_CTRL);
+ }
+}
+
+static void aspeed_jtag_xfer_push_data_last(struct aspeed_jtag *aspeed_jtag,
+ enum jtag_xfer_type type,
+ u32 shift_bits,
+ enum jtag_endstate endstate)
+{
+ if (endstate == JTAG_STATE_IDLE) {
+ if (type == JTAG_SIR_XFER) {
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_INST_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_instruction_pause(aspeed_jtag);
+ } else {
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_DR_UPDATE,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_DR_UPDATE |
+ ASPEED_JTAG_CTL_DATA_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_data_pause_complete(aspeed_jtag);
+ }
+ } else {
+ if (type == JTAG_SIR_XFER) {
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_INST,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_INST |
+ ASPEED_JTAG_CTL_INST_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_instruction_complete(aspeed_jtag);
+ } else {
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_DATA,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_DATA |
+ ASPEED_JTAG_CTL_DATA_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_data_complete(aspeed_jtag);
+ }
+ }
+}
+
+static void aspeed_jtag_xfer_hw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_xfer *xfer, u32 *data)
+{
+ unsigned long remain_xfer = xfer->length;
+ unsigned long index = 0;
+ char shift_bits;
+ u32 data_reg;
+
+ data_reg = xfer->type == JTAG_SIR_XFER ?
+ ASPEED_JTAG_INST : ASPEED_JTAG_DATA;
+ while (remain_xfer) {
+ if (xfer->direction == JTAG_WRITE_XFER)
+ aspeed_jtag_write(aspeed_jtag, data[index], data_reg);
+ else
+ aspeed_jtag_write(aspeed_jtag, 0, data_reg);
+
+ if (remain_xfer > ASPEED_JTAG_DATA_CHUNK_SIZE) {
+ shift_bits = ASPEED_JTAG_DATA_CHUNK_SIZE;
+
+ /*
+ * Read bytes were not equals to column length
+ * and go to Pause-DR
+ */
+ aspeed_jtag_xfer_push_data(aspeed_jtag, xfer->type,
+ shift_bits);
+ } else {
+ /*
+ * Read bytes equals to column length =>
+ * Update-DR
+ */
+ shift_bits = remain_xfer;
+ aspeed_jtag_xfer_push_data_last(aspeed_jtag, xfer->type,
+ shift_bits,
+ xfer->endstate);
+ }
+
+ if (xfer->direction == JTAG_READ_XFER) {
+ if (shift_bits < ASPEED_JTAG_DATA_CHUNK_SIZE) {
+ data[index] = aspeed_jtag_read(aspeed_jtag,
+ data_reg);
+
+ data[index] >>= ASPEED_JTAG_DATA_CHUNK_SIZE -
+ shift_bits;
+ } else {
+ data[index] = aspeed_jtag_read(aspeed_jtag,
+ data_reg);
+ }
+ }
+
+ remain_xfer = remain_xfer - shift_bits;
+ index++;
+ }
+}
+
+static int aspeed_jtag_xfer(struct jtag *jtag, struct jtag_xfer *xfer,
+ u8 *xfer_data)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ dev_dbg(aspeed_jtag->dev, "xfer %s\n",
+ xfer->type == JTAG_SIR_XFER ? "SIR" : "SDR");
+
+ if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) {
+ /* SW mode */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_TDIO, ASPEED_JTAG_SW);
+
+ aspeed_jtag_xfer_sw(aspeed_jtag, xfer, (u32 *)xfer_data);
+ } else {
+ /* HW mode */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW);
+ aspeed_jtag_xfer_hw(aspeed_jtag, xfer, (u32 *)xfer_data);
+ }
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_TDIO, ASPEED_JTAG_SW);
+ aspeed_jtag->status = xfer->endstate;
+ return 0;
+}
+
+static int aspeed_jtag_status_get(struct jtag *jtag, u32 *status)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ *status = aspeed_jtag->status;
+ return 0;
+}
+
+static irqreturn_t aspeed_jtag_interrupt(s32 this_irq, void *dev_id)
+{
+ struct aspeed_jtag *aspeed_jtag = dev_id;
+ irqreturn_t ret;
+ u32 status;
+
+ status = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_ISR);
+
+ if (status & ASPEED_JTAG_ISR_INT_MASK) {
+ aspeed_jtag_write(aspeed_jtag,
+ (status & ASPEED_JTAG_ISR_INT_MASK)
+ | (status & ASPEED_JTAG_ISR_INT_EN_MASK),
+ ASPEED_JTAG_ISR);
+ aspeed_jtag->flag |= status & ASPEED_JTAG_ISR_INT_MASK;
+ }
+
+ if (aspeed_jtag->flag) {
+ wake_up_interruptible(&aspeed_jtag->jtag_wq);
+ ret = IRQ_HANDLED;
+ } else {
+ dev_err(aspeed_jtag->dev, "irq status:%x\n",
+ status);
+ ret = IRQ_NONE;
+ }
+ return ret;
+}
+
+static int aspeed_jtag_init(struct platform_device *pdev,
+ struct aspeed_jtag *aspeed_jtag)
+{
+ struct resource *res;
+ int err;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ aspeed_jtag->reg_base = devm_ioremap_resource(aspeed_jtag->dev, res);
+ if (IS_ERR(aspeed_jtag->reg_base))
+ return -ENOMEM;
+
+ aspeed_jtag->pclk = devm_clk_get(aspeed_jtag->dev, NULL);
+ if (IS_ERR(aspeed_jtag->pclk)) {
+ dev_err(aspeed_jtag->dev, "devm_clk_get failed\n");
+ return PTR_ERR(aspeed_jtag->pclk);
+ }
+
+ aspeed_jtag->irq = platform_get_irq(pdev, 0);
+ if (aspeed_jtag->irq < 0) {
+ dev_err(aspeed_jtag->dev, "no irq specified\n");
+ return -ENOENT;
+ }
+
+ if (clk_prepare_enable(aspeed_jtag->pclk)) {
+ dev_err(aspeed_jtag->dev, "no irq specified\n");
+ return -ENOENT;
+ }
+
+ aspeed_jtag->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
+ if (IS_ERR(aspeed_jtag->rst)) {
+ dev_err(aspeed_jtag->dev,
+ "missing or invalid reset controller device tree entry");
+ return PTR_ERR(aspeed_jtag->rst);
+ }
+ reset_control_deassert(aspeed_jtag->rst);
+
+ /* Enable clock */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_CTL_ENG_EN |
+ ASPEED_JTAG_CTL_ENG_OUT_EN, ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_TDIO, ASPEED_JTAG_SW);
+
+ err = devm_request_irq(aspeed_jtag->dev, aspeed_jtag->irq,
+ aspeed_jtag_interrupt, 0,
+ "aspeed-jtag", aspeed_jtag);
+ if (err) {
+ dev_err(aspeed_jtag->dev, "unable to get IRQ");
+ goto clk_unprep;
+ }
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_ISR_INST_PAUSE |
+ ASPEED_JTAG_ISR_INST_COMPLETE |
+ ASPEED_JTAG_ISR_DATA_PAUSE |
+ ASPEED_JTAG_ISR_DATA_COMPLETE |
+ ASPEED_JTAG_ISR_INST_PAUSE_EN |
+ ASPEED_JTAG_ISR_INST_COMPLETE_EN |
+ ASPEED_JTAG_ISR_DATA_PAUSE_EN |
+ ASPEED_JTAG_ISR_DATA_COMPLETE_EN,
+ ASPEED_JTAG_ISR);
+
+ aspeed_jtag->flag = 0;
+ aspeed_jtag->mode = 0;
+ init_waitqueue_head(&aspeed_jtag->jtag_wq);
+ return 0;
+
+clk_unprep:
+ clk_disable_unprepare(aspeed_jtag->pclk);
+ return err;
+}
+
+static int aspeed_jtag_deinit(struct platform_device *pdev,
+ struct aspeed_jtag *aspeed_jtag)
+{
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_ISR);
+ /* Disable clock */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_CTRL);
+ reset_control_assert(aspeed_jtag->rst);
+ clk_disable_unprepare(aspeed_jtag->pclk);
+ return 0;
+}
+
+static const struct jtag_ops aspeed_jtag_ops = {
+ .freq_get = aspeed_jtag_freq_get,
+ .freq_set = aspeed_jtag_freq_set,
+ .status_get = aspeed_jtag_status_get,
+ .idle = aspeed_jtag_idle,
+ .xfer = aspeed_jtag_xfer,
+ .mode_set = aspeed_jtag_mode_set
+};
+
+static int aspeed_jtag_probe(struct platform_device *pdev)
+{
+ struct aspeed_jtag *aspeed_jtag;
+ struct jtag *jtag;
+ int err;
+
+ jtag = jtag_alloc(&pdev->dev, sizeof(*aspeed_jtag), &aspeed_jtag_ops);
+ if (!jtag)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, jtag);
+ aspeed_jtag = jtag_priv(jtag);
+ aspeed_jtag->dev = &pdev->dev;
+
+ /* Initialize device*/
+ err = aspeed_jtag_init(pdev, aspeed_jtag);
+ if (err)
+ goto err_jtag_init;
+
+ /* Initialize JTAG core structure*/
+ err = devm_jtag_register(aspeed_jtag->dev, jtag);
+ if (err)
+ goto err_jtag_register;
+
+ return 0;
+
+err_jtag_register:
+ aspeed_jtag_deinit(pdev, aspeed_jtag);
+err_jtag_init:
+ jtag_free(jtag);
+ return err;
+}
+
+static int aspeed_jtag_remove(struct platform_device *pdev)
+{
+ struct jtag *jtag = platform_get_drvdata(pdev);
+
+ aspeed_jtag_deinit(pdev, jtag_priv(jtag));
+ return 0;
+}
+
+static const struct of_device_id aspeed_jtag_of_match[] = {
+ { .compatible = "aspeed,ast2400-jtag", },
+ { .compatible = "aspeed,ast2500-jtag", },
+ {}
+};
+
+static struct platform_driver aspeed_jtag_driver = {
+ .probe = aspeed_jtag_probe,
+ .remove = aspeed_jtag_remove,
+ .driver = {
+ .name = ASPEED_JTAG_NAME,
+ .of_match_table = aspeed_jtag_of_match,
+ },
+};
+module_platform_driver(aspeed_jtag_driver);
+
+MODULE_AUTHOR("Oleksandr Shamray <oleksandrs@mellanox.com>");
+MODULE_DESCRIPTION("ASPEED JTAG driver");
+MODULE_LICENSE("GPL v2");
--
1.7.1
^ permalink raw reply related
* [patch v26 1/4] drivers: jtag: Add JTAG core driver
From: Oleksandr Shamray @ 2018-06-15 16:45 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, vadimp, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray
In-Reply-To: <1529081123-30873-1-git-send-email-oleksandrs@mellanox.com>
Initial patch for JTAG driver
JTAG class driver provide infrastructure to support hardware/software
JTAG platform drivers. It provide user layer API interface for flashing
and debugging external devices which equipped with JTAG interface
using standard transactions.
Driver exposes set of IOCTL to user space for:
- XFER:
- SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
- SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks).
- SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
---
v24->v25
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- set values to enums in jtag.h
v23->v24
Notifications from kbuild test robot <lkp@intel.com>
- Add include types.h header to jtag.h
- remove unecessary jtag_release
v22->v23
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- remove restriction of allocated JTAG devs-
- add validation fo idle values
- remove unnecessary blank line
- change retcode for xfer
- remove unecessary jtag_release callback
- remove unecessary defined fron jtag.h
- align in one line define JTAG_IOCRUNTEST
v21->v22
Comments pointed by Andy Shevchenko <andy.shevchenko@gmail.com>
- Fix 0x0f -> 0x0F in ioctl-number.txt
- Add description to #define MAX_JTAG_NAME_LEN
- Remove unnecessary entry *dev from struct jtag
- Remove redundant parens
- Described mandatory callbacks and removed unnecessary
- Set JTAG_MAX_XFER_DATA_LEN to power of 2
- rework driver alloc/register to devm_ variant
- increasing line length up to 84 in order to improve readability.
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- fix spell in ABI doccumentation
v20->v21
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Fix JTAG dirver help in Kconfig
v19->v20
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Fix JTAG dirver help in Kconfig
Notifications from kbuild test robot <lkp@intel.com>
- fix incompatible type casts
v18->v19
Comments pointed by Julia Cartwright <juliac@eso.teric.us>
- Fix memory leak on jtag_alloc exit
v17->v18
Comments pointed by Julia Cartwright <juliac@eso.teric.us>
- Change to return -EOPNOTSUPP in case of error in JTAG_GIOCFREQ
- Add ops callbacks check to jtag_alloc
- Add err check for copy_to_user
- Move the kfree() above the if (err) in JTAG_IOCXFER
- remove unnecessary check for error after put_user
- add padding to struct jtag_xfer
v16->v17
Comments pointed by Julia Cartwright <juliac@eso.teric.us>
- Fix memory allocation on jtag alloc
- Move out unnecessary form lock on jtag open
- Rework jtag register behavior
v15->v16
Comments pointed by Florian Fainelli <f.fainelli@gmail.com>
- move check jtag->ops->* in ioctl before get_user()
- change error type -EINVAL --> -EBUSY on open already opened jtag
- remove unnecessary ARCH_DMA_MINALIGN flag from kzalloc
- remove define ARCH_DMA_MINALIGN
v14->v15
v13->v14
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change style of head block comment from /**/ to //
v12->v13
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change jtag.c licence type to
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
and reorder line with license in description
v11->v12
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- Change jtag.h licence type to
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
and reorder line with license in description
Comments pointed by Chip Bilbrey <chip@bilbrey.org>
- Remove Apeed reference from uapi jtag.h header
- Remove access mode from xfer and idle transactions
- Add new ioctl JTAG_SIOCMODE for set hw mode
- Add single open per device blocking
v10->v11
Notifications from kbuild test robot <lkp@intel.com>
- Add include types.h header to jtag.h
- fix incompatible type of xfer callback
- remove rdundant class defination
- Fix return order in case of xfer error
V9->v10
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- remove unnecessary alignment for pirv data
- move jtag_copy_to_user and jtag_copy_from_user code just to ioctl
- move int jtag_run_test_idle_op and jtag_xfer_op code
just to ioctl
- change return error codes to more applicable
- add missing error checks
- fix error check order in ioctl
- remove unnecessary blank lines
- add param validation to ioctl
- remove compat_ioctl
- remove only one open per JTAG port blocking.
User will care about this.
- Fix idr memory leak on jtag_exit
- change cdev device type to misc
V8->v9
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- use get_user() instead of __get_user().
- change jtag->open type from int to atomic_t
- remove spinlock on jtg_open
- remove mutex on jtag_register
- add unregister_chrdev_region on jtag_init err
- add unregister_chrdev_region on jtag_exit
- remove unnecessary pointer casts
- add *data parameter to xfer function prototype
v7->v8
Comments pointed by Moritz Fischer <moritz.fischer@ettus.com>
- Fix misspelling s/friver/driver
v6->v7
Notifications from kbuild test robot <lkp@intel.com>
- Remove include asm/types.h from jtag.h
- Add include <linux/types.h> to jtag.c
v5->v6
v4->v5
v3->v4
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- change transaction pointer tdio type to __u64
- change internal status type from enum to __u32
- reorder jtag_xfer members to avoid the implied padding
- add __packed attribute to jtag_xfer and jtag_run_test_idle
v2->v3
Notifications from kbuild test robot <lkp@intel.com>
- Change include path to <linux/types.h> in jtag.h
v1->v2
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- Change license type from GPLv2/BSD to GPLv2
- Change type of variables which crossed user/kernel to __type
- Remove "default n" from Kconfig
Comments pointed by Andrew Lunn <andrew@lunn.ch>
- Change list_add_tail in jtag_unregister to list_del
Comments pointed by Neil Armstrong <narmstrong@baylibre.com>
- Add SPDX-License-Identifier instead of license text
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- Change __copy_to_user to memdup_user
- Change __put_user to put_user
- Change type of variables to __type for compatible 32 and 64-bit systems
- Add check for maximum xfer data size
- Change lookup data mechanism to get jtag data from inode
- Add .compat_ioctl to file ops
- Add mem alignment for jtag priv data
Comments pointed by Tobias Klauser <tklauser@distanz.ch>
- Change function names to avoid match with variable types
- Fix description for jtag_ru_test_idle in uapi jtag.h
- Fix misprints IDEL/IDLE, trough/through
---
Documentation/ioctl/ioctl-number.txt | 2 +
MAINTAINERS | 8 +
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/jtag/Kconfig | 17 ++
drivers/jtag/Makefile | 1 +
drivers/jtag/jtag.c | 274 ++++++++++++++++++++++++++++++++++
include/linux/jtag.h | 41 +++++
include/uapi/linux/jtag.h | 109 ++++++++++++++
9 files changed, 455 insertions(+), 0 deletions(-)
create mode 100644 drivers/jtag/Kconfig
create mode 100644 drivers/jtag/Makefile
create mode 100644 drivers/jtag/jtag.c
create mode 100644 include/linux/jtag.h
create mode 100644 include/uapi/linux/jtag.h
diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt
index 7f7413e..886e676 100644
--- a/Documentation/ioctl/ioctl-number.txt
+++ b/Documentation/ioctl/ioctl-number.txt
@@ -318,6 +318,8 @@ Code Seq#(hex) Include File Comments
0xB0 all RATIO devices in development:
<mailto:vgo@ratio.de>
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
+0xB2 00-0F linux/jtag.h JTAG driver
+ <mailto:oleksandrs@mellanox.com>
0xB3 00 linux/mmc/ioctl.h
0xB4 00-0F linux/gpio.h <mailto:linux-gpio@vger.kernel.org>
0xB5 00-0F uapi/linux/rpmsg.h <mailto:linux-remoteproc@vger.kernel.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 79bb02f..e7b8b2c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7610,6 +7610,14 @@ L: linux-serial@vger.kernel.org
S: Maintained
F: drivers/tty/serial/jsm/
+JTAG SUBSYSTEM
+M: Oleksandr Shamray <oleksandrs@mellanox.com>
+M: Vadim Pasternak <vadimp@mellanox.com>
+S: Maintained
+F: include/linux/jtag.h
+F: include/uapi/linux/jtag.h
+F: drivers/jtag/
+
K10TEMP HARDWARE MONITORING DRIVER
M: Clemens Ladisch <clemens@ladisch.de>
L: linux-hwmon@vger.kernel.org
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 95b9ccc..bb71e48 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -217,4 +217,6 @@ source "drivers/siox/Kconfig"
source "drivers/slimbus/Kconfig"
+source "drivers/jtag/Kconfig"
+
endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 24cd470..c92636b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -185,3 +185,4 @@ obj-$(CONFIG_TEE) += tee/
obj-$(CONFIG_MULTIPLEXER) += mux/
obj-$(CONFIG_UNISYS_VISORBUS) += visorbus/
obj-$(CONFIG_SIOX) += siox/
+obj-$(CONFIG_JTAG) += jtag/
diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig
new file mode 100644
index 0000000..47771fc
--- /dev/null
+++ b/drivers/jtag/Kconfig
@@ -0,0 +1,17 @@
+menuconfig JTAG
+ tristate "JTAG support"
+ help
+ This provides basic core functionality support for JTAG class devices.
+ Hardware that is equipped with a JTAG microcontroller can be
+ supported by using this driver's interfaces.
+ This driver exposes a set of IOCTLs to the user space for
+ the following commands:
+ SDR: Performs an IEEE 1149.1 Data Register scan
+ SIR: Performs an IEEE 1149.1 Instruction Register scan.
+ RUNTEST: Forces the IEEE 1149.1 bus to a run state for a specified
+ number of clocks or a specified time period.
+
+ If you want this support, you should say Y here.
+
+ To compile this driver as a module, choose M here: the module will
+ be called jtag.
diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
new file mode 100644
index 0000000..af37493
--- /dev/null
+++ b/drivers/jtag/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_JTAG) += jtag.o
diff --git a/drivers/jtag/jtag.c b/drivers/jtag/jtag.c
new file mode 100644
index 0000000..6657b84
--- /dev/null
+++ b/drivers/jtag/jtag.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// drivers/jtag/jtag.c
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/jtag.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/rtnetlink.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <uapi/linux/jtag.h>
+
+struct jtag {
+ struct miscdevice miscdev;
+ const struct jtag_ops *ops;
+ int id;
+ unsigned long priv[0];
+};
+
+static DEFINE_IDA(jtag_ida);
+
+void *jtag_priv(struct jtag *jtag)
+{
+ return jtag->priv;
+}
+EXPORT_SYMBOL_GPL(jtag_priv);
+
+static long jtag_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ struct jtag *jtag = file->private_data;
+ struct jtag_run_test_idle idle;
+ struct jtag_xfer xfer;
+ u8 *xfer_data;
+ u32 data_size;
+ u32 value;
+ int err;
+
+ if (!arg)
+ return -EINVAL;
+
+ switch (cmd) {
+ case JTAG_GIOCFREQ:
+ if (!jtag->ops->freq_get)
+ return -EOPNOTSUPP;
+
+ err = jtag->ops->freq_get(jtag, &value);
+ if (err)
+ break;
+
+ if (put_user(value, (__u32 __user *)arg))
+ err = -EFAULT;
+ break;
+
+ case JTAG_SIOCFREQ:
+ if (!jtag->ops->freq_set)
+ return -EOPNOTSUPP;
+
+ if (get_user(value, (__u32 __user *)arg))
+ return -EFAULT;
+ if (value == 0)
+ return -EINVAL;
+
+ err = jtag->ops->freq_set(jtag, value);
+ break;
+
+ case JTAG_IOCRUNTEST:
+ if (copy_from_user(&idle, (const void __user *)arg,
+ sizeof(struct jtag_run_test_idle)))
+ return -EFAULT;
+
+ if (idle.endstate > JTAG_STATE_PAUSEDR)
+ return -EINVAL;
+
+ if (idle.reset > JTAG_FORCE_RESET)
+ return -EINVAL;
+
+ err = jtag->ops->idle(jtag, &idle);
+ break;
+
+ case JTAG_IOCXFER:
+ if (copy_from_user(&xfer, (const void __user *)arg,
+ sizeof(struct jtag_xfer)))
+ return -EFAULT;
+
+ if (xfer.length >= JTAG_MAX_XFER_DATA_LEN)
+ return -EINVAL;
+
+ if (xfer.type > JTAG_SDR_XFER)
+ return -EINVAL;
+
+ if (xfer.direction > JTAG_WRITE_XFER)
+ return -EINVAL;
+
+ if (xfer.endstate > JTAG_STATE_PAUSEDR)
+ return -EINVAL;
+
+ data_size = DIV_ROUND_UP(xfer.length, BITS_PER_BYTE);
+ xfer_data = memdup_user(u64_to_user_ptr(xfer.tdio), data_size);
+ if (IS_ERR(xfer_data))
+ return -EFAULT;
+
+ err = jtag->ops->xfer(jtag, &xfer, xfer_data);
+ if (err) {
+ kfree(xfer_data);
+ return err;
+ }
+
+ err = copy_to_user(u64_to_user_ptr(xfer.tdio),
+ (void *)xfer_data, data_size);
+ kfree(xfer_data);
+ if (err)
+ return -EFAULT;
+
+ if (copy_to_user((void __user *)arg, (void *)&xfer,
+ sizeof(struct jtag_xfer)))
+ return -EFAULT;
+ break;
+
+ case JTAG_GIOCSTATUS:
+ err = jtag->ops->status_get(jtag, &value);
+ if (err)
+ break;
+
+ err = put_user(value, (__u32 __user *)arg);
+ break;
+ case JTAG_SIOCMODE:
+ if (!jtag->ops->mode_set)
+ return -EOPNOTSUPP;
+
+ if (get_user(value, (__u32 __user *)arg))
+ return -EFAULT;
+ if (value == 0)
+ return -EINVAL;
+
+ err = jtag->ops->mode_set(jtag, value);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ return err;
+}
+
+static int jtag_open(struct inode *inode, struct file *file)
+{
+ struct jtag *jtag = container_of(file->private_data, struct jtag, miscdev);
+
+ file->private_data = jtag;
+ return nonseekable_open(inode, file);
+}
+
+static const struct file_operations jtag_fops = {
+ .owner = THIS_MODULE,
+ .open = jtag_open,
+ .llseek = noop_llseek,
+ .unlocked_ioctl = jtag_ioctl,
+};
+
+struct jtag *jtag_alloc(struct device *host, size_t priv_size,
+ const struct jtag_ops *ops)
+{
+ struct jtag *jtag;
+
+ if (!host)
+ return NULL;
+
+ if (!ops)
+ return NULL;
+
+ if (!ops->idle || !ops->status_get || !ops->xfer)
+ return NULL;
+
+ jtag = kzalloc(sizeof(*jtag) + priv_size, GFP_KERNEL);
+ if (!jtag)
+ return NULL;
+
+ jtag->ops = ops;
+ jtag->miscdev.parent = host;
+
+ return jtag;
+}
+EXPORT_SYMBOL_GPL(jtag_alloc);
+
+void jtag_free(struct jtag *jtag)
+{
+ kfree(jtag);
+}
+EXPORT_SYMBOL_GPL(jtag_free);
+
+static int jtag_register(struct jtag *jtag)
+{
+ struct device *dev = jtag->miscdev.parent;
+ int err;
+ int id;
+
+ if (!dev)
+ return -ENODEV;
+
+ id = ida_simple_get(&jtag_ida, 0, 0, GFP_KERNEL);
+ if (id < 0)
+ return id;
+
+ jtag->id = id;
+
+ jtag->miscdev.fops = &jtag_fops;
+ jtag->miscdev.minor = MISC_DYNAMIC_MINOR;
+ jtag->miscdev.name = kasprintf(GFP_KERNEL, "jtag%d", id);
+ if (!jtag->miscdev.name) {
+ err = -ENOMEM;
+ goto err_jtag_alloc;
+ }
+
+ err = misc_register(&jtag->miscdev);
+ if (err) {
+ dev_err(jtag->miscdev.parent, "Unable to register device\n");
+ goto err_jtag_name;
+ }
+ return 0;
+
+err_jtag_name:
+ kfree(jtag->miscdev.name);
+err_jtag_alloc:
+ ida_simple_remove(&jtag_ida, id);
+ return err;
+}
+
+static void jtag_unregister(struct jtag *jtag)
+{
+ misc_deregister(&jtag->miscdev);
+ kfree(jtag->miscdev.name);
+ ida_simple_remove(&jtag_ida, jtag->id);
+}
+
+static void devm_jtag_unregister(struct device *dev, void *res)
+{
+ jtag_unregister(*(struct jtag **)res);
+}
+
+int devm_jtag_register(struct device *dev, struct jtag *jtag)
+{
+ struct jtag **ptr;
+ int ret;
+
+ ptr = devres_alloc(devm_jtag_unregister, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return -ENOMEM;
+
+ ret = jtag_register(jtag);
+ if (!ret) {
+ *ptr = jtag;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+ return ret;
+}
+EXPORT_SYMBOL_GPL(devm_jtag_register);
+
+static void __exit jtag_exit(void)
+{
+ ida_destroy(&jtag_ida);
+}
+
+module_exit(jtag_exit);
+
+MODULE_AUTHOR("Oleksandr Shamray <oleksandrs@mellanox.com>");
+MODULE_DESCRIPTION("Generic jtag support");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/jtag.h b/include/linux/jtag.h
new file mode 100644
index 0000000..fd5dd79
--- /dev/null
+++ b/include/linux/jtag.h
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+// include/linux/jtag.h - JTAG class driver
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#ifndef __JTAG_H
+#define __JTAG_H
+
+#include <linux/types.h>
+#include <uapi/linux/jtag.h>
+
+#define JTAG_MAX_XFER_DATA_LEN 65535
+
+struct jtag;
+/**
+ * struct jtag_ops - callbacks for JTAG control functions:
+ *
+ * @freq_get: get frequency function. Filled by dev driver
+ * @freq_set: set frequency function. Filled by dev driver
+ * @status_get: set status function. Mandatory func. Filled by dev driver
+ * @idle: set JTAG to idle state function. Mandatory func. Filled by dev driver
+ * @xfer: send JTAG xfer function. Mandatory func. Filled by dev driver
+ * @mode_set: set specific work mode for JTAG. Filled by dev driver
+ */
+struct jtag_ops {
+ int (*freq_get)(struct jtag *jtag, u32 *freq);
+ int (*freq_set)(struct jtag *jtag, u32 freq);
+ int (*status_get)(struct jtag *jtag, u32 *state);
+ int (*idle)(struct jtag *jtag, struct jtag_run_test_idle *idle);
+ int (*xfer)(struct jtag *jtag, struct jtag_xfer *xfer, u8 *xfer_data);
+ int (*mode_set)(struct jtag *jtag, u32 mode_mask);
+};
+
+void *jtag_priv(struct jtag *jtag);
+int devm_jtag_register(struct device *dev, struct jtag *jtag);
+struct jtag *jtag_alloc(struct device *host, size_t priv_size,
+ const struct jtag_ops *ops);
+void jtag_free(struct jtag *jtag);
+
+#endif /* __JTAG_H */
diff --git a/include/uapi/linux/jtag.h b/include/uapi/linux/jtag.h
new file mode 100644
index 0000000..4f521b8
--- /dev/null
+++ b/include/uapi/linux/jtag.h
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+// include/uapi/linux/jtag.h - JTAG class driver uapi
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#ifndef __UAPI_LINUX_JTAG_H
+#define __UAPI_LINUX_JTAG_H
+
+/*
+ * JTAG_XFER_HW_MODE: JTAG hardware mode. Used to set HW drived or bitbang
+ * mode. This is bitmask param of ioctl JTAG_SIOCMODE command
+ */
+#define JTAG_XFER_HW_MODE 1
+
+/**
+ * enum jtag_endstate:
+ *
+ * @JTAG_STATE_IDLE: JTAG state machine IDLE state
+ * @JTAG_STATE_PAUSEIR: JTAG state machine PAUSE_IR state
+ * @JTAG_STATE_PAUSEDR: JTAG state machine PAUSE_DR state
+ */
+enum jtag_endstate {
+ JTAG_STATE_IDLE = 0,
+ JTAG_STATE_PAUSEIR = 1,
+ JTAG_STATE_PAUSEDR = 2,
+};
+
+/**
+ * enum jtag_reset:
+ *
+ * @JTAG_NO_RESET: JTAG run TAP from current state
+ * @JTAG_FORCE_RESET: JTAG force TAP to reset state
+ */
+enum jtag_reset {
+ JTAG_NO_RESET = 0,
+ JTAG_FORCE_RESET = 1,
+};
+
+/**
+ * enum jtag_xfer_type:
+ *
+ * @JTAG_SIR_XFER: SIR transfer
+ * @JTAG_SDR_XFER: SDR transfer
+ */
+enum jtag_xfer_type {
+ JTAG_SIR_XFER = 0,
+ JTAG_SDR_XFER = 1,
+};
+
+/**
+ * enum jtag_xfer_direction:
+ *
+ * @JTAG_READ_XFER: read transfer
+ * @JTAG_WRITE_XFER: write transfer
+ */
+enum jtag_xfer_direction {
+ JTAG_READ_XFER = 0,
+ JTAG_WRITE_XFER = 1,
+};
+
+/**
+ * struct jtag_run_test_idle - forces JTAG state machine to
+ * RUN_TEST/IDLE state
+ *
+ * @reset: 0 - run IDLE/PAUSE from current state
+ * 1 - go through TEST_LOGIC/RESET state before IDLE/PAUSE
+ * @end: completion flag
+ * @tck: clock counter
+ *
+ * Structure provide interface to JTAG device for JTAG IDLE execution.
+ */
+struct jtag_run_test_idle {
+ __u8 reset;
+ __u8 endstate;
+ __u8 tck;
+};
+
+/**
+ * struct jtag_xfer - jtag xfer:
+ *
+ * @type: transfer type
+ * @direction: xfer direction
+ * @length: xfer bits len
+ * @tdio : xfer data array
+ * @endir: xfer end state
+ *
+ * Structure provide interface to JTAG device for JTAG SDR/SIR xfer execution.
+ */
+struct jtag_xfer {
+ __u8 type;
+ __u8 direction;
+ __u8 endstate;
+ __u8 padding;
+ __u32 length;
+ __u64 tdio;
+};
+
+/* ioctl interface */
+#define __JTAG_IOCTL_MAGIC 0xb2
+
+#define JTAG_IOCRUNTEST _IOW(__JTAG_IOCTL_MAGIC, 0, struct jtag_run_test_idle)
+#define JTAG_SIOCFREQ _IOW(__JTAG_IOCTL_MAGIC, 1, unsigned int)
+#define JTAG_GIOCFREQ _IOR(__JTAG_IOCTL_MAGIC, 2, unsigned int)
+#define JTAG_IOCXFER _IOWR(__JTAG_IOCTL_MAGIC, 3, struct jtag_xfer)
+#define JTAG_GIOCSTATUS _IOWR(__JTAG_IOCTL_MAGIC, 4, enum jtag_endstate)
+#define JTAG_SIOCMODE _IOW(__JTAG_IOCTL_MAGIC, 5, unsigned int)
+
+#endif /* __UAPI_LINUX_JTAG_H */
--
1.7.1
^ permalink raw reply related
* [patch v26 0/4] JTAG driver introduction
From: Oleksandr Shamray @ 2018-06-15 16:45 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, vadimp, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray
When a need raise up to use JTAG interface for system's devices
programming or CPU debugging, usually the user layer
application implements jtag protocol by bit-bang or using a
proprietary connection to vendor hardware.
This method can be slow and not generic.
We propose to implement general JTAG interface and infrastructure
to communicate with user layer application. In such way, we can
have the standard JTAG interface core part and separation from
specific HW implementation.
This allow new capability to debug the CPU or program system's
device via BMC without additional devices nor cost.
This patch purpose is to add JTAG master core infrastructure by
defining new JTAG class and provide generic JTAG interface
to allow hardware specific drivers to connect this interface.
This will enable all JTAG drivers to use the common interface
part and will have separate for hardware implementation.
The JTAG (Joint Test Action Group) core driver provides minimal generic
JTAG interface, which can be used by hardware specific JTAG master
controllers. By providing common interface for the JTAG controllers,
user space device programing is hardware independent.
Modern SoC which in use for embedded system' equipped with
internal JTAG master interface.
This interface is used for programming and debugging system's
hardware components, like CPLD, FPGA, CPU, voltage and
industrial controllers.
Firmware for such devices can be upgraded through JTAG interface during
Runtime. The JTAG standard support for multiple devices programming,
is in case their lines are daisy-chained together.
For example, systems which equipped with host CPU, BMC SoC or/and
number of programmable devices are capable to connect a pin and
select system components dynamically for programming and debugging,
This is using by the BMC which is equipped with internal SoC master
controller.
For example:
BMC JTAG master --> pin selected to CPLDs chain for programming (filed
upgrade, production)
BMC JTAG master --> pin selected to voltage monitors for programming
(field upgrade, production)
BMC JTAG master --> pin selected to host CPU (on-site debugging
and developers debugging)
For example, we can have application in user space which using calls
to JTAG driver executes CPLD programming directly from SVF file
The JTAG standard (IEEE 1149.1) defines the next connector pins:
- TDI (Test Data In);
- TDO (Test Data Out);
- TCK (Test Clock);
- TMS (Test Mode Select);
- TRST (Test Reset) (Optional);
The SoC equipped with JTAG master controller, performs
device programming on command or vector level. For example
a file in a standard SVF (Serial Vector Format) that contains
boundary scan vectors, can be used by sending each vector
to the JTAG interface and the JTAG controller will execute
the programming.
Initial version provides the system calls set for:
- SIR (Scan Instruction Register, IEEE 1149.1 Instruction Register scan);
- SDR (Scan Data Register, IEEE 1149.1 Data Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardware specific driver.
Oleksandr Shamray (4):
drivers: jtag: Add JTAG core driver
drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master
driver
Documentation: jtag: Add bindings for Aspeed SoC 24xx and 25xx
families JTAG master driver
Documentation: jtag: Add ABI documentation
Documentation/ABI/testing/gpio-cdev | 1 -
Documentation/ABI/testing/jtag-dev | 23 +
.../devicetree/bindings/jtag/aspeed-jtag.txt | 22 +
Documentation/ioctl/ioctl-number.txt | 2 +
Documentation/jtag/overview | 27 +
Documentation/jtag/transactions | 109 +++
MAINTAINERS | 10 +
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/jtag/Kconfig | 31 +
drivers/jtag/Makefile | 2 +
drivers/jtag/jtag-aspeed.c | 756 ++++++++++++++++++++
drivers/jtag/jtag.c | 274 +++++++
include/linux/jtag.h | 41 ++
include/uapi/linux/jtag.h | 109 +++
15 files changed, 1409 insertions(+), 1 deletions(-)
create mode 100644 Documentation/ABI/testing/jtag-dev
create mode 100644 Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
create mode 100644 Documentation/jtag/overview
create mode 100644 Documentation/jtag/transactions
create mode 100644 drivers/jtag/Kconfig
create mode 100644 drivers/jtag/Makefile
create mode 100644 drivers/jtag/jtag-aspeed.c
create mode 100644 drivers/jtag/jtag.c
create mode 100644 include/linux/jtag.h
create mode 100644 include/uapi/linux/jtag.h
^ permalink raw reply
* Re: [PATCH v6 17/29] fpga: dfl: fme: add partial reconfiguration sub feature support
From: Wu Hao @ 2018-06-15 5:52 UTC (permalink / raw)
To: Alan Tull
Cc: Moritz Fischer, linux-fpga, linux-kernel, linux-api, Kang, Luwei,
Zhang, Yi Z, Tim Whisonant, Enno Luebbers, Shiva Rao,
Christopher Rauer, Xiao Guangrong
In-Reply-To: <CANk1AXRU9yXhgWu9_CZLLRQfNKedR22ghoPLGeTRUeTX24XtWw@mail.gmail.com>
On Thu, Jun 14, 2018 at 11:33:00AM -0500, Alan Tull wrote:
> On Wed, Jun 13, 2018 at 8:07 PM, Moritz Fischer <mdf@kernel.org> wrote:
>
> Hellooo,
>
> This probably could use a comment, please see below.
>
> > Hi,
> >
> > quick question for Alan inline below.
> >
>
> >> +static int fme_pr(struct platform_device *pdev, unsigned long arg)
> >> +{
> >> + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> >> + void __user *argp = (void __user *)arg;
> >> + struct dfl_fpga_fme_port_pr port_pr;
> >> + struct fpga_image_info *info;
> >> + struct fpga_region *region;
> >> + void __iomem *fme_hdr;
> >> + struct dfl_fme *fme;
> >> + unsigned long minsz;
> >> + void *buf = NULL;
> >> + int ret = 0;
> >> + u64 v;
> >> +
> >> + minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address);
> >> +
> >> + if (copy_from_user(&port_pr, argp, minsz))
> >> + return -EFAULT;
> >> +
> >> + if (port_pr.argsz < minsz || port_pr.flags)
> >> + return -EINVAL;
> >> +
> >> + if (!IS_ALIGNED(port_pr.buffer_size, 4))
> >> + return -EINVAL;
> >> +
> >> + /* get fme header region */
> >> + fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
> >> + FME_FEATURE_ID_HEADER);
> >> +
> >> + /* check port id */
> >> + v = readq(fme_hdr + FME_HDR_CAP);
> >> + if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) {
> >> + dev_dbg(&pdev->dev, "port number more than maximum\n");
> >> + return -EINVAL;
> >> + }
> >> +
> >> + if (!access_ok(VERIFY_READ,
> >> + (void __user *)(unsigned long)port_pr.buffer_address,
> >> + port_pr.buffer_size))
> >> + return -EFAULT;
> >> +
> >> + buf = vmalloc(port_pr.buffer_size);
> >> + if (!buf)
> >> + return -ENOMEM;
> >> +
> >> + if (copy_from_user(buf,
> >> + (void __user *)(unsigned long)port_pr.buffer_address,
> >> + port_pr.buffer_size)) {
> >> + ret = -EFAULT;
> >> + goto free_exit;
> >> + }
> >> +
> >> + /* prepare fpga_image_info for PR */
> >> + info = fpga_image_info_alloc(&pdev->dev);
> >> + if (!info) {
> >> + ret = -ENOMEM;
> >> + goto free_exit;
> >> + }
> >> +
> >> + info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
> >> +
> >> + mutex_lock(&pdata->lock);
> >> + fme = dfl_fpga_pdata_get_private(pdata);
> >> + /* fme device has been unregistered. */
> >> + if (!fme) {
> >> + ret = -EINVAL;
> >> + goto unlock_exit;
> >> + }
> >> +
> >> + region = dfl_fme_region_find(fme, port_pr.port_id);
> >> + if (!region) {
> >> + ret = -EINVAL;
> >> + goto unlock_exit;
> >> + }
> >> +
> >> + fpga_image_info_free(region->info);
> >> +
> >> + info->buf = buf;
> >> + info->count = port_pr.buffer_size;
> >> + info->region_id = port_pr.port_id;
> >> + region->info = info;
> >> +
> >> + ret = fpga_region_program_fpga(region);
> >> +
> >> + if (region->get_bridges)
> >> + fpga_bridges_put(®ion->bridge_list);
> >
> > I'm wondering if this should not be done as part of
> > fpga_region_program_fpga() (It's not at the moment).
> >
> > Alan, am I missing something obvious? :)
>
> It is up to the caller of fpga_region_program_fpga to put the bridges
> before programming again. That prevents something other than the
> caller from reprogramming a partial region or messing with the bridges
> until the caller puts the bridges.
>
> For example, for DT support, applying an overlay calls
> fpga_region_program_fpga() which gets the bridges, disables them, does
> the programming, and reenables the bridges. Then the bridges are
> held, preventing anything else from disabling the bridges until the
> overlay is removed. This was important in the DT case since the
> overlay could include child nodes for hardware in the FPGA. Allowing
> anyone else to play with the bridges while those drivers were
> expecting hardware access could be bad.
>
> I can't remember for certain, but I think this code has to put the
> bridges here because this patch set allows userspace to reset the PR
> region's logic by disabling/reenabling the bridge to clear things out
> between acceleration runs (which Hao promises is OK to do, it's
> documented elsewhere in the pachset). It probably could use a comment
> right here to explain why the bridges are put here so future
> generations know not to break this.
Yes, it's correct. I can add some comments here in the next version.
Thanks
Hao
>
> Alan
>
> >> +
> >> + put_device(®ion->dev);
> >> +unlock_exit:
> >> + mutex_unlock(&pdata->lock);
> >> +free_exit:
> >> + vfree(buf);
> >> + if (copy_to_user((void __user *)arg, &port_pr, minsz))
> >> + return -EFAULT;
> >> +
> >> + return ret;
> >> +}
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fpga" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v6 17/29] fpga: dfl: fme: add partial reconfiguration sub feature support
From: Alan Tull @ 2018-06-14 16:33 UTC (permalink / raw)
To: Moritz Fischer
Cc: Wu Hao, linux-fpga, linux-kernel, linux-api, Kang, Luwei,
Zhang, Yi Z, Tim Whisonant, Enno Luebbers, Shiva Rao,
Christopher Rauer, Xiao Guangrong
In-Reply-To: <20180614010713.fivl64pirawrnrhc@derp-derp.local>
On Wed, Jun 13, 2018 at 8:07 PM, Moritz Fischer <mdf@kernel.org> wrote:
Hellooo,
This probably could use a comment, please see below.
> Hi,
>
> quick question for Alan inline below.
>
>> +static int fme_pr(struct platform_device *pdev, unsigned long arg)
>> +{
>> + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
>> + void __user *argp = (void __user *)arg;
>> + struct dfl_fpga_fme_port_pr port_pr;
>> + struct fpga_image_info *info;
>> + struct fpga_region *region;
>> + void __iomem *fme_hdr;
>> + struct dfl_fme *fme;
>> + unsigned long minsz;
>> + void *buf = NULL;
>> + int ret = 0;
>> + u64 v;
>> +
>> + minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address);
>> +
>> + if (copy_from_user(&port_pr, argp, minsz))
>> + return -EFAULT;
>> +
>> + if (port_pr.argsz < minsz || port_pr.flags)
>> + return -EINVAL;
>> +
>> + if (!IS_ALIGNED(port_pr.buffer_size, 4))
>> + return -EINVAL;
>> +
>> + /* get fme header region */
>> + fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
>> + FME_FEATURE_ID_HEADER);
>> +
>> + /* check port id */
>> + v = readq(fme_hdr + FME_HDR_CAP);
>> + if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) {
>> + dev_dbg(&pdev->dev, "port number more than maximum\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (!access_ok(VERIFY_READ,
>> + (void __user *)(unsigned long)port_pr.buffer_address,
>> + port_pr.buffer_size))
>> + return -EFAULT;
>> +
>> + buf = vmalloc(port_pr.buffer_size);
>> + if (!buf)
>> + return -ENOMEM;
>> +
>> + if (copy_from_user(buf,
>> + (void __user *)(unsigned long)port_pr.buffer_address,
>> + port_pr.buffer_size)) {
>> + ret = -EFAULT;
>> + goto free_exit;
>> + }
>> +
>> + /* prepare fpga_image_info for PR */
>> + info = fpga_image_info_alloc(&pdev->dev);
>> + if (!info) {
>> + ret = -ENOMEM;
>> + goto free_exit;
>> + }
>> +
>> + info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
>> +
>> + mutex_lock(&pdata->lock);
>> + fme = dfl_fpga_pdata_get_private(pdata);
>> + /* fme device has been unregistered. */
>> + if (!fme) {
>> + ret = -EINVAL;
>> + goto unlock_exit;
>> + }
>> +
>> + region = dfl_fme_region_find(fme, port_pr.port_id);
>> + if (!region) {
>> + ret = -EINVAL;
>> + goto unlock_exit;
>> + }
>> +
>> + fpga_image_info_free(region->info);
>> +
>> + info->buf = buf;
>> + info->count = port_pr.buffer_size;
>> + info->region_id = port_pr.port_id;
>> + region->info = info;
>> +
>> + ret = fpga_region_program_fpga(region);
>> +
>> + if (region->get_bridges)
>> + fpga_bridges_put(®ion->bridge_list);
>
> I'm wondering if this should not be done as part of
> fpga_region_program_fpga() (It's not at the moment).
>
> Alan, am I missing something obvious? :)
It is up to the caller of fpga_region_program_fpga to put the bridges
before programming again. That prevents something other than the
caller from reprogramming a partial region or messing with the bridges
until the caller puts the bridges.
For example, for DT support, applying an overlay calls
fpga_region_program_fpga() which gets the bridges, disables them, does
the programming, and reenables the bridges. Then the bridges are
held, preventing anything else from disabling the bridges until the
overlay is removed. This was important in the DT case since the
overlay could include child nodes for hardware in the FPGA. Allowing
anyone else to play with the bridges while those drivers were
expecting hardware access could be bad.
I can't remember for certain, but I think this code has to put the
bridges here because this patch set allows userspace to reset the PR
region's logic by disabling/reenabling the bridge to clear things out
between acceleration runs (which Hao promises is OK to do, it's
documented elsewhere in the pachset). It probably could use a comment
right here to explain why the bridges are put here so future
generations know not to break this.
Alan
>> +
>> + put_device(®ion->dev);
>> +unlock_exit:
>> + mutex_unlock(&pdata->lock);
>> +free_exit:
>> + vfree(buf);
>> + if (copy_to_user((void __user *)arg, &port_pr, minsz))
>> + return -EFAULT;
>> +
>> + return ret;
>> +}
^ permalink raw reply
* Re: [PATCH v6 18/29] fpga: dfl: add fpga manager platform driver for FME
From: Wu Hao @ 2018-06-14 13:50 UTC (permalink / raw)
To: Moritz Fischer
Cc: atull, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang, Tim Whisonant, Enno Luebbers, Shiva Rao,
Christopher Rauer, Xiao Guangrong
In-Reply-To: <20180614011642.scearqx5glmffuwc@derp-derp.local>
On Wed, Jun 13, 2018 at 08:16:42PM -0500, Moritz Fischer wrote:
> Hi Hao,
>
> small nit below, looks good otherwise.
>
> On Tue, Jun 12, 2018 at 06:10:32PM +0800, Wu Hao wrote:
> > This patch adds fpga manager driver for FPGA Management Engine (FME). It
> > implements fpga_manager_ops for FPGA Partial Reconfiguration function.
> >
> > Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
> > Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
> > Signed-off-by: Shiva Rao <shiva.rao@intel.com>
> > Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
> > Signed-off-by: Kang Luwei <luwei.kang@intel.com>
> > Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> > Signed-off-by: Wu Hao <hao.wu@intel.com>
> > Acked-by: Alan Tull <atull@kernel.org>
> > ---
> > v3: rename driver to dfl-fpga-fme-mgr
> > implemented status callback for fpga manager
> > rebased due to fpga api changes
> > v4: rename to dfl-fme-mgr, and fix SPDX license issue
> > add pr_credit comments and improve dev_err message
> > remove interface_id sysfs interface
> > include dfl-fme-pr.h instead of dfl.h
> > v5: move related register definition from dfl-fme-pr.h to dfl-fme-mgr.c
> > use mapped ioaddr passed via pdata for register access.
> > rebase due to fpga manager API changes.
> > include header file for readq/writeq.
> > v6: rebase, fix copyright time and add Acked-by from Alan.
> > ---
> > drivers/fpga/Kconfig | 6 +
> > drivers/fpga/Makefile | 1 +
> > drivers/fpga/dfl-fme-mgr.c | 334 +++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 341 insertions(+)
> > create mode 100644 drivers/fpga/dfl-fme-mgr.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index 45e9220..ca97f3c 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -156,6 +156,12 @@ config FPGA_DFL_FME
> > FPGA platform level management features. There shall be 1 FME
> > per DFL based FPGA device.
> >
> > +config FPGA_DFL_FME_MGR
> > + tristate "FPGA DFL FME Manager Driver"
> > + depends on FPGA_DFL_FME
> > + help
> > + Say Y to enable FPGA Manager driver for FPGA Management Engine.
> > +
> > config FPGA_DFL_PCI
> > tristate "FPGA DFL PCIe Device Driver"
> > depends on PCI && FPGA_DFL
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > index fd334d40..23f41b0 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -32,6 +32,7 @@ obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
> > # FPGA Device Feature List Support
> > obj-$(CONFIG_FPGA_DFL) += dfl.o
> > obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
> > +obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
> >
> > dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
> >
> > diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c
> > new file mode 100644
> > index 0000000..be0060a
> > --- /dev/null
> > +++ b/drivers/fpga/dfl-fme-mgr.c
> > @@ -0,0 +1,334 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * FPGA Manager Driver for FPGA Management Engine (FME)
> > + *
> > + * Copyright (C) 2017-2018 Intel Corporation, Inc.
> > + *
> > + * Authors:
> > + * Kang Luwei <luwei.kang@intel.com>
> > + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> > + * Wu Hao <hao.wu@intel.com>
> > + * Joseph Grecco <joe.grecco@intel.com>
> > + * Enno Luebbers <enno.luebbers@intel.com>
> > + * Tim Whisonant <tim.whisonant@intel.com>
> > + * Ananda Ravuri <ananda.ravuri@intel.com>
> > + * Christopher Rauer <christopher.rauer@intel.com>
> > + * Henry Mitchel <henry.mitchel@intel.com>
> > + */
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/module.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/io-64-nonatomic-lo-hi.h>
> > +#include <linux/fpga/fpga-mgr.h>
> > +
> > +#include "dfl-fme-pr.h"
> > +
> > +/* FME Partial Reconfiguration Sub Feature Register Set */
> > +#define FME_PR_DFH 0x0
> > +#define FME_PR_CTRL 0x8
> > +#define FME_PR_STS 0x10
> > +#define FME_PR_DATA 0x18
> > +#define FME_PR_ERR 0x20
> > +#define FME_PR_INTFC_ID_H 0xA8
> > +#define FME_PR_INTFC_ID_L 0xB0
> > +
> > +/* FME PR Control Register Bitfield */
> > +#define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */
> > +#define FME_PR_CTRL_PR_RSTACK BIT_ULL(4) /* Ack for PR engine reset */
> > +#define FME_PR_CTRL_PR_RGN_ID GENMASK_ULL(9, 7) /* PR Region ID */
> > +#define FME_PR_CTRL_PR_START BIT_ULL(12) /* Start to request PR service */
> > +#define FME_PR_CTRL_PR_COMPLETE BIT_ULL(13) /* PR data push completion */
> > +
> > +/* FME PR Status Register Bitfield */
> > +/* Number of available entries in HW queue inside the PR engine. */
> > +#define FME_PR_STS_PR_CREDIT GENMASK_ULL(8, 0)
> > +#define FME_PR_STS_PR_STS BIT_ULL(16) /* PR operation status */
> > +#define FME_PR_STS_PR_STS_IDLE 0
> > +#define FME_PR_STS_PR_CTRLR_STS GENMASK_ULL(22, 20) /* Controller status */
> > +#define FME_PR_STS_PR_HOST_STS GENMASK_ULL(27, 24) /* PR host status */
> > +
> > +/* FME PR Data Register Bitfield */
> > +/* PR data from the raw-binary file. */
> > +#define FME_PR_DATA_PR_DATA_RAW GENMASK_ULL(32, 0)
> > +
> > +/* FME PR Error Register */
> > +/* PR Operation errors detected. */
> > +#define FME_PR_ERR_OPERATION_ERR BIT_ULL(0)
> > +/* CRC error detected. */
> > +#define FME_PR_ERR_CRC_ERR BIT_ULL(1)
> > +/* Incompatible PR bitstream detected. */
> > +#define FME_PR_ERR_INCOMPATIBLE_BS BIT_ULL(2)
> > +/* PR data push protocol violated. */
> > +#define FME_PR_ERR_PROTOCOL_ERR BIT_ULL(3)
> > +/* PR data fifo overflow error detected */
> > +#define FME_PR_ERR_FIFO_OVERFLOW BIT_ULL(4)
> > +
> > +#define PR_WAIT_TIMEOUT 8000000
> > +#define PR_HOST_STATUS_IDLE 0
> > +
> > +struct fme_mgr_priv {
> > + void __iomem *ioaddr;
> > + u64 pr_error;
> > +};
> > +
> > +static u64 pr_error_to_mgr_status(u64 err)
> > +{
> > + u64 status = 0;
> > +
> > + if (err & FME_PR_ERR_OPERATION_ERR)
> > + status |= FPGA_MGR_STATUS_OPERATION_ERR;
> > + if (err & FME_PR_ERR_CRC_ERR)
> > + status |= FPGA_MGR_STATUS_CRC_ERR;
> > + if (err & FME_PR_ERR_INCOMPATIBLE_BS)
> > + status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR;
> > + if (err & FME_PR_ERR_PROTOCOL_ERR)
> > + status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR;
> > + if (err & FME_PR_ERR_FIFO_OVERFLOW)
> > + status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR;
> > +
> > + return status;
> > +}
> > +
> > +static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr)
> > +{
> > + u64 pr_status, pr_error;
> > +
> > + pr_status = readq(fme_pr + FME_PR_STS);
> > + if (!(pr_status & FME_PR_STS_PR_STS))
> > + return 0;
> > +
> > + pr_error = readq(fme_pr + FME_PR_ERR);
> > + writeq(pr_error, fme_pr + FME_PR_ERR);
> > +
> > + return pr_error;
> > +}
> > +
> > +static int fme_mgr_write_init(struct fpga_manager *mgr,
> > + struct fpga_image_info *info,
> > + const char *buf, size_t count)
> > +{
> > + struct device *dev = &mgr->dev;
> > + struct fme_mgr_priv *priv = mgr->priv;
> > + void __iomem *fme_pr = priv->ioaddr;
> > + u64 pr_ctrl, pr_status;
> > +
> > + if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
> > + dev_err(dev, "only supports partial reconfiguration.\n");
> > + return -EINVAL;
> > + }
> > +
> > + dev_dbg(dev, "resetting PR before initiated PR\n");
> > +
> > + pr_ctrl = readq(fme_pr + FME_PR_CTRL);
> > + pr_ctrl |= FME_PR_CTRL_PR_RST;
> > + writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
> > +
> > + if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
> > + pr_ctrl & FME_PR_CTRL_PR_RSTACK, 1,
> > + PR_WAIT_TIMEOUT)) {
> > + dev_err(dev, "PR Reset ACK timeout\n");
> > + return -ETIMEDOUT;
> > + }
> > +
> > + pr_ctrl = readq(fme_pr + FME_PR_CTRL);
> > + pr_ctrl &= ~FME_PR_CTRL_PR_RST;
> > + writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
> > +
> > + dev_dbg(dev,
> > + "waiting for PR resource in HW to be initialized and ready\n");
> > +
> > + if (readq_poll_timeout(fme_pr + FME_PR_STS, pr_status,
> > + (pr_status & FME_PR_STS_PR_STS) ==
> > + FME_PR_STS_PR_STS_IDLE, 1, PR_WAIT_TIMEOUT)) {
> > + dev_err(dev, "PR Status timeout\n");
> > + priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
> > + return -ETIMEDOUT;
> > + }
> > +
> > + dev_dbg(dev, "check and clear previous PR error\n");
> > + priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
> > + if (priv->pr_error)
> > + dev_dbg(dev, "previous PR error detected %llx\n",
> > + (unsigned long long)priv->pr_error);
> > +
> > + dev_dbg(dev, "set PR port ID\n");
> > +
> > + pr_ctrl = readq(fme_pr + FME_PR_CTRL);
> > + pr_ctrl &= ~FME_PR_CTRL_PR_RGN_ID;
> > + pr_ctrl |= FIELD_PREP(FME_PR_CTRL_PR_RGN_ID, info->region_id);
> > + writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
> > +
> > + return 0;
> > +}
> > +
> > +static int fme_mgr_write(struct fpga_manager *mgr,
> > + const char *buf, size_t count)
> > +{
> > + struct device *dev = &mgr->dev;
> > + struct fme_mgr_priv *priv = mgr->priv;
> > + void __iomem *fme_pr = priv->ioaddr;
> > + u64 pr_ctrl, pr_status, pr_data;
> > + int delay = 0, pr_credit, i = 0;
> > +
> > + dev_dbg(dev, "start request\n");
> > +
> > + pr_ctrl = readq(fme_pr + FME_PR_CTRL);
> > + pr_ctrl |= FME_PR_CTRL_PR_START;
> > + writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
> > +
> > + dev_dbg(dev, "pushing data from bitstream to HW\n");
> > +
> > + /*
> > + * driver can push data to PR hardware using PR_DATA register once HW
> > + * has enough pr_credit (> 1), pr_credit reduces one for every 32bit
> > + * pr data write to PR_DATA register. If pr_credit <= 1, driver needs
> > + * to wait for enough pr_credit from hardware by polling.
> > + */
> > + pr_status = readq(fme_pr + FME_PR_STS);
> > + pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
> > +
> > + while (count > 0) {
> > + while (pr_credit <= 1) {
> > + if (delay++ > PR_WAIT_TIMEOUT) {
> > + dev_err(dev, "PR_CREDIT timeout\n");
> > + return -ETIMEDOUT;
> > + }
> > + udelay(1);
> > +
> > + pr_status = readq(fme_pr + FME_PR_STS);
> > + pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
> > + }
> > +
> > + if (count < 4) {
> > + WARN_ON(1);
> Maybe an error message instead of WARN_ON()? How about "Invalid PR
> bitstream size" ?
Sure, will change this in the next version.
Hao
> Thanks,
>
> Moritz
^ permalink raw reply
* Re: [PATCH v6 18/29] fpga: dfl: add fpga manager platform driver for FME
From: Moritz Fischer @ 2018-06-14 1:16 UTC (permalink / raw)
To: Wu Hao
Cc: atull, mdf, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang, Tim Whisonant, Enno Luebbers, Shiva Rao,
Christopher Rauer, Xiao Guangrong
In-Reply-To: <1528798243-2029-19-git-send-email-hao.wu@intel.com>
Hi Hao,
small nit below, looks good otherwise.
On Tue, Jun 12, 2018 at 06:10:32PM +0800, Wu Hao wrote:
> This patch adds fpga manager driver for FPGA Management Engine (FME). It
> implements fpga_manager_ops for FPGA Partial Reconfiguration function.
>
> Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
> Signed-off-by: Shiva Rao <shiva.rao@intel.com>
> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
> Signed-off-by: Kang Luwei <luwei.kang@intel.com>
> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Alan Tull <atull@kernel.org>
> ---
> v3: rename driver to dfl-fpga-fme-mgr
> implemented status callback for fpga manager
> rebased due to fpga api changes
> v4: rename to dfl-fme-mgr, and fix SPDX license issue
> add pr_credit comments and improve dev_err message
> remove interface_id sysfs interface
> include dfl-fme-pr.h instead of dfl.h
> v5: move related register definition from dfl-fme-pr.h to dfl-fme-mgr.c
> use mapped ioaddr passed via pdata for register access.
> rebase due to fpga manager API changes.
> include header file for readq/writeq.
> v6: rebase, fix copyright time and add Acked-by from Alan.
> ---
> drivers/fpga/Kconfig | 6 +
> drivers/fpga/Makefile | 1 +
> drivers/fpga/dfl-fme-mgr.c | 334 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 341 insertions(+)
> create mode 100644 drivers/fpga/dfl-fme-mgr.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 45e9220..ca97f3c 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -156,6 +156,12 @@ config FPGA_DFL_FME
> FPGA platform level management features. There shall be 1 FME
> per DFL based FPGA device.
>
> +config FPGA_DFL_FME_MGR
> + tristate "FPGA DFL FME Manager Driver"
> + depends on FPGA_DFL_FME
> + help
> + Say Y to enable FPGA Manager driver for FPGA Management Engine.
> +
> config FPGA_DFL_PCI
> tristate "FPGA DFL PCIe Device Driver"
> depends on PCI && FPGA_DFL
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index fd334d40..23f41b0 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -32,6 +32,7 @@ obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
> # FPGA Device Feature List Support
> obj-$(CONFIG_FPGA_DFL) += dfl.o
> obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
> +obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
>
> dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
>
> diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c
> new file mode 100644
> index 0000000..be0060a
> --- /dev/null
> +++ b/drivers/fpga/dfl-fme-mgr.c
> @@ -0,0 +1,334 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * FPGA Manager Driver for FPGA Management Engine (FME)
> + *
> + * Copyright (C) 2017-2018 Intel Corporation, Inc.
> + *
> + * Authors:
> + * Kang Luwei <luwei.kang@intel.com>
> + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> + * Wu Hao <hao.wu@intel.com>
> + * Joseph Grecco <joe.grecco@intel.com>
> + * Enno Luebbers <enno.luebbers@intel.com>
> + * Tim Whisonant <tim.whisonant@intel.com>
> + * Ananda Ravuri <ananda.ravuri@intel.com>
> + * Christopher Rauer <christopher.rauer@intel.com>
> + * Henry Mitchel <henry.mitchel@intel.com>
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/module.h>
> +#include <linux/iopoll.h>
> +#include <linux/io-64-nonatomic-lo-hi.h>
> +#include <linux/fpga/fpga-mgr.h>
> +
> +#include "dfl-fme-pr.h"
> +
> +/* FME Partial Reconfiguration Sub Feature Register Set */
> +#define FME_PR_DFH 0x0
> +#define FME_PR_CTRL 0x8
> +#define FME_PR_STS 0x10
> +#define FME_PR_DATA 0x18
> +#define FME_PR_ERR 0x20
> +#define FME_PR_INTFC_ID_H 0xA8
> +#define FME_PR_INTFC_ID_L 0xB0
> +
> +/* FME PR Control Register Bitfield */
> +#define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */
> +#define FME_PR_CTRL_PR_RSTACK BIT_ULL(4) /* Ack for PR engine reset */
> +#define FME_PR_CTRL_PR_RGN_ID GENMASK_ULL(9, 7) /* PR Region ID */
> +#define FME_PR_CTRL_PR_START BIT_ULL(12) /* Start to request PR service */
> +#define FME_PR_CTRL_PR_COMPLETE BIT_ULL(13) /* PR data push completion */
> +
> +/* FME PR Status Register Bitfield */
> +/* Number of available entries in HW queue inside the PR engine. */
> +#define FME_PR_STS_PR_CREDIT GENMASK_ULL(8, 0)
> +#define FME_PR_STS_PR_STS BIT_ULL(16) /* PR operation status */
> +#define FME_PR_STS_PR_STS_IDLE 0
> +#define FME_PR_STS_PR_CTRLR_STS GENMASK_ULL(22, 20) /* Controller status */
> +#define FME_PR_STS_PR_HOST_STS GENMASK_ULL(27, 24) /* PR host status */
> +
> +/* FME PR Data Register Bitfield */
> +/* PR data from the raw-binary file. */
> +#define FME_PR_DATA_PR_DATA_RAW GENMASK_ULL(32, 0)
> +
> +/* FME PR Error Register */
> +/* PR Operation errors detected. */
> +#define FME_PR_ERR_OPERATION_ERR BIT_ULL(0)
> +/* CRC error detected. */
> +#define FME_PR_ERR_CRC_ERR BIT_ULL(1)
> +/* Incompatible PR bitstream detected. */
> +#define FME_PR_ERR_INCOMPATIBLE_BS BIT_ULL(2)
> +/* PR data push protocol violated. */
> +#define FME_PR_ERR_PROTOCOL_ERR BIT_ULL(3)
> +/* PR data fifo overflow error detected */
> +#define FME_PR_ERR_FIFO_OVERFLOW BIT_ULL(4)
> +
> +#define PR_WAIT_TIMEOUT 8000000
> +#define PR_HOST_STATUS_IDLE 0
> +
> +struct fme_mgr_priv {
> + void __iomem *ioaddr;
> + u64 pr_error;
> +};
> +
> +static u64 pr_error_to_mgr_status(u64 err)
> +{
> + u64 status = 0;
> +
> + if (err & FME_PR_ERR_OPERATION_ERR)
> + status |= FPGA_MGR_STATUS_OPERATION_ERR;
> + if (err & FME_PR_ERR_CRC_ERR)
> + status |= FPGA_MGR_STATUS_CRC_ERR;
> + if (err & FME_PR_ERR_INCOMPATIBLE_BS)
> + status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR;
> + if (err & FME_PR_ERR_PROTOCOL_ERR)
> + status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR;
> + if (err & FME_PR_ERR_FIFO_OVERFLOW)
> + status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR;
> +
> + return status;
> +}
> +
> +static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr)
> +{
> + u64 pr_status, pr_error;
> +
> + pr_status = readq(fme_pr + FME_PR_STS);
> + if (!(pr_status & FME_PR_STS_PR_STS))
> + return 0;
> +
> + pr_error = readq(fme_pr + FME_PR_ERR);
> + writeq(pr_error, fme_pr + FME_PR_ERR);
> +
> + return pr_error;
> +}
> +
> +static int fme_mgr_write_init(struct fpga_manager *mgr,
> + struct fpga_image_info *info,
> + const char *buf, size_t count)
> +{
> + struct device *dev = &mgr->dev;
> + struct fme_mgr_priv *priv = mgr->priv;
> + void __iomem *fme_pr = priv->ioaddr;
> + u64 pr_ctrl, pr_status;
> +
> + if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
> + dev_err(dev, "only supports partial reconfiguration.\n");
> + return -EINVAL;
> + }
> +
> + dev_dbg(dev, "resetting PR before initiated PR\n");
> +
> + pr_ctrl = readq(fme_pr + FME_PR_CTRL);
> + pr_ctrl |= FME_PR_CTRL_PR_RST;
> + writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
> +
> + if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
> + pr_ctrl & FME_PR_CTRL_PR_RSTACK, 1,
> + PR_WAIT_TIMEOUT)) {
> + dev_err(dev, "PR Reset ACK timeout\n");
> + return -ETIMEDOUT;
> + }
> +
> + pr_ctrl = readq(fme_pr + FME_PR_CTRL);
> + pr_ctrl &= ~FME_PR_CTRL_PR_RST;
> + writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
> +
> + dev_dbg(dev,
> + "waiting for PR resource in HW to be initialized and ready\n");
> +
> + if (readq_poll_timeout(fme_pr + FME_PR_STS, pr_status,
> + (pr_status & FME_PR_STS_PR_STS) ==
> + FME_PR_STS_PR_STS_IDLE, 1, PR_WAIT_TIMEOUT)) {
> + dev_err(dev, "PR Status timeout\n");
> + priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
> + return -ETIMEDOUT;
> + }
> +
> + dev_dbg(dev, "check and clear previous PR error\n");
> + priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
> + if (priv->pr_error)
> + dev_dbg(dev, "previous PR error detected %llx\n",
> + (unsigned long long)priv->pr_error);
> +
> + dev_dbg(dev, "set PR port ID\n");
> +
> + pr_ctrl = readq(fme_pr + FME_PR_CTRL);
> + pr_ctrl &= ~FME_PR_CTRL_PR_RGN_ID;
> + pr_ctrl |= FIELD_PREP(FME_PR_CTRL_PR_RGN_ID, info->region_id);
> + writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
> +
> + return 0;
> +}
> +
> +static int fme_mgr_write(struct fpga_manager *mgr,
> + const char *buf, size_t count)
> +{
> + struct device *dev = &mgr->dev;
> + struct fme_mgr_priv *priv = mgr->priv;
> + void __iomem *fme_pr = priv->ioaddr;
> + u64 pr_ctrl, pr_status, pr_data;
> + int delay = 0, pr_credit, i = 0;
> +
> + dev_dbg(dev, "start request\n");
> +
> + pr_ctrl = readq(fme_pr + FME_PR_CTRL);
> + pr_ctrl |= FME_PR_CTRL_PR_START;
> + writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
> +
> + dev_dbg(dev, "pushing data from bitstream to HW\n");
> +
> + /*
> + * driver can push data to PR hardware using PR_DATA register once HW
> + * has enough pr_credit (> 1), pr_credit reduces one for every 32bit
> + * pr data write to PR_DATA register. If pr_credit <= 1, driver needs
> + * to wait for enough pr_credit from hardware by polling.
> + */
> + pr_status = readq(fme_pr + FME_PR_STS);
> + pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
> +
> + while (count > 0) {
> + while (pr_credit <= 1) {
> + if (delay++ > PR_WAIT_TIMEOUT) {
> + dev_err(dev, "PR_CREDIT timeout\n");
> + return -ETIMEDOUT;
> + }
> + udelay(1);
> +
> + pr_status = readq(fme_pr + FME_PR_STS);
> + pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
> + }
> +
> + if (count < 4) {
> + WARN_ON(1);
Maybe an error message instead of WARN_ON()? How about "Invalid PR
bitstream size" ?
> + return -EINVAL;
> + }
> +
> + pr_data = 0;
> + pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
> + *(((u32 *)buf) + i));
> + writeq(pr_data, fme_pr + FME_PR_DATA);
> + count -= 4;
> + pr_credit--;
> + i++;
> + }
> +
> + return 0;
> +}
> +
> +static int fme_mgr_write_complete(struct fpga_manager *mgr,
> + struct fpga_image_info *info)
> +{
> + struct device *dev = &mgr->dev;
> + struct fme_mgr_priv *priv = mgr->priv;
> + void __iomem *fme_pr = priv->ioaddr;
> + u64 pr_ctrl;
> +
> + pr_ctrl = readq(fme_pr + FME_PR_CTRL);
> + pr_ctrl |= FME_PR_CTRL_PR_COMPLETE;
> + writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
> +
> + dev_dbg(dev, "green bitstream push complete\n");
> + dev_dbg(dev, "waiting for HW to release PR resource\n");
> +
> + if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
> + !(pr_ctrl & FME_PR_CTRL_PR_START), 1,
> + PR_WAIT_TIMEOUT)) {
> + dev_err(dev, "PR Completion ACK timeout.\n");
> + return -ETIMEDOUT;
> + }
> +
> + dev_dbg(dev, "PR operation complete, checking status\n");
> + priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
> + if (priv->pr_error) {
> + dev_dbg(dev, "PR error detected %llx\n",
> + (unsigned long long)priv->pr_error);
> + return -EIO;
> + }
> +
> + dev_dbg(dev, "PR done successfully\n");
> +
> + return 0;
> +}
> +
> +static enum fpga_mgr_states fme_mgr_state(struct fpga_manager *mgr)
> +{
> + return FPGA_MGR_STATE_UNKNOWN;
> +}
> +
> +static u64 fme_mgr_status(struct fpga_manager *mgr)
> +{
> + struct fme_mgr_priv *priv = mgr->priv;
> +
> + return pr_error_to_mgr_status(priv->pr_error);
> +}
> +
> +static const struct fpga_manager_ops fme_mgr_ops = {
> + .write_init = fme_mgr_write_init,
> + .write = fme_mgr_write,
> + .write_complete = fme_mgr_write_complete,
> + .state = fme_mgr_state,
> + .status = fme_mgr_status,
> +};
> +
> +static int fme_mgr_probe(struct platform_device *pdev)
> +{
> + struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);
> + struct device *dev = &pdev->dev;
> + struct fme_mgr_priv *priv;
> + struct fpga_manager *mgr;
> + struct resource *res;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + if (pdata->ioaddr)
> + priv->ioaddr = pdata->ioaddr;
> +
> + if (!priv->ioaddr) {
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->ioaddr = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->ioaddr))
> + return PTR_ERR(priv->ioaddr);
> + }
> +
> + mgr = fpga_mgr_create(dev, "DFL FME FPGA Manager",
> + &fme_mgr_ops, priv);
> + if (!mgr)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, mgr);
> +
> + ret = fpga_mgr_register(mgr);
> + if (ret)
> + fpga_mgr_free(mgr);
> +
> + return ret;
> +}
> +
> +static int fme_mgr_remove(struct platform_device *pdev)
> +{
> + struct fpga_manager *mgr = platform_get_drvdata(pdev);
> +
> + fpga_mgr_unregister(mgr);
> +
> + return 0;
> +}
> +
> +static struct platform_driver fme_mgr_driver = {
> + .driver = {
> + .name = DFL_FPGA_FME_MGR,
> + },
> + .probe = fme_mgr_probe,
> + .remove = fme_mgr_remove,
> +};
> +
> +module_platform_driver(fme_mgr_driver);
> +
> +MODULE_DESCRIPTION("FPGA Manager for DFL FPGA Management Engine");
> +MODULE_AUTHOR("Intel Corporation");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:dfl-fme-mgr");
> --
> 1.8.3.1
>
Thanks,
Moritz
^ permalink raw reply
* Re: [PATCH v6 17/29] fpga: dfl: fme: add partial reconfiguration sub feature support
From: Moritz Fischer @ 2018-06-14 1:07 UTC (permalink / raw)
To: Wu Hao
Cc: atull, mdf, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang, Tim Whisonant, Enno Luebbers, Shiva Rao,
Christopher Rauer, Xiao Guangrong
In-Reply-To: <1528798243-2029-18-git-send-email-hao.wu@intel.com>
Hi,
quick question for Alan inline below.
On Tue, Jun 12, 2018 at 06:10:31PM +0800, Wu Hao wrote:
> From: Kang Luwei <luwei.kang@intel.com>
>
> Partial Reconfiguration (PR) is the most important function for FME. It
> allows reconfiguration for given Port/Accelerated Function Unit (AFU).
>
> It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges,
> and invokes fpga-region's interface (fpga_region_program_fpga) for PR
> operation once PR request received via ioctl. Below user space interface
> is exposed by this sub feature.
>
> Ioctl interface:
> * DFL_FPGA_FME_PORT_PR
> Do partial reconfiguration per information from userspace, including
> target port(AFU), buffer size and address info. It returns error code
> to userspace if failed. For detailed PR error information, user needs
> to read fpga-mgr's status sysfs interface.
>
> Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
> Signed-off-by: Shiva Rao <shiva.rao@intel.com>
> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
> Signed-off-by: Kang Luwei <luwei.kang@intel.com>
> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Alan Tull <atull@kernel.org>
> ---
> v2: moved the code to drivers/fpga folder as suggested by Alan Tull.
> switched to GPLv2 license.
> removed status from FPGA_FME_PORT_PR ioctl data structure.
> added platform devices creation for fpga-mgr/fpga-region/fpga-bridge.
> switched to fpga-region interface fpga_region_program_fpga for PR.
> fixed comments from Alan Tull on FPGA_MGR_PARTIAL_RECONFIG flag usage.
> fixed kbuild warnings.
> v3: rename driver files to dfl-fme-*.
> rebase due to fpga APIs change.
> replace bitfields.
> switch to fpga_cdev_find_port to find port device.
> v4: rebase and correct comments for some function.
> fix SPDX license issue.
> remove unnecessary input parameter for destroy_bridge/region function.
> add dfl-fme-pr.h for PR sub feature data structure and registers.
> v5: rebase due to DFL framework API naming changes.
> improve naming for IOCTL API, functions and data structure.
> defer finding port platform device to fme bridge.
> pass mapped ioaddr to fme manager via pdata.
> remove useless devm_kfree().
> v6: rebase, fix copyright time and improve function name.
> add Acked-by from Alan.
> ---
> drivers/fpga/Makefile | 2 +-
> drivers/fpga/dfl-fme-main.c | 43 +++-
> drivers/fpga/dfl-fme-pr.c | 474 ++++++++++++++++++++++++++++++++++++++++++
> drivers/fpga/dfl-fme-pr.h | 84 ++++++++
> drivers/fpga/dfl-fme.h | 38 ++++
> include/uapi/linux/fpga-dfl.h | 28 +++
> 6 files changed, 667 insertions(+), 2 deletions(-)
> create mode 100644 drivers/fpga/dfl-fme-pr.c
> create mode 100644 drivers/fpga/dfl-fme-pr.h
> create mode 100644 drivers/fpga/dfl-fme.h
>
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index db11f34..fd334d40 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -33,7 +33,7 @@ obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
> obj-$(CONFIG_FPGA_DFL) += dfl.o
> obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
>
> -dfl-fme-objs := dfl-fme-main.o
> +dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
>
> # Drivers for FPGAs which implement DFL
> obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
> index 889d669..7359804 100644
> --- a/drivers/fpga/dfl-fme-main.c
> +++ b/drivers/fpga/dfl-fme-main.c
> @@ -19,6 +19,7 @@
> #include <linux/fpga-dfl.h>
>
> #include "dfl.h"
> +#include "dfl-fme.h"
>
> static ssize_t ports_num_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> @@ -113,6 +114,10 @@ static void fme_hdr_uinit(struct platform_device *pdev,
> .ops = &fme_hdr_ops,
> },
> {
> + .id = FME_FEATURE_ID_PR_MGMT,
> + .ops = &pr_mgmt_ops,
> + },
> + {
> .ops = NULL,
> },
> };
> @@ -187,6 +192,35 @@ static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
> return -EINVAL;
> }
>
> +static int fme_dev_init(struct platform_device *pdev)
> +{
> + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> + struct dfl_fme *fme;
> +
> + fme = devm_kzalloc(&pdev->dev, sizeof(*fme), GFP_KERNEL);
> + if (!fme)
> + return -ENOMEM;
> +
> + fme->pdata = pdata;
> +
> + mutex_lock(&pdata->lock);
> + dfl_fpga_pdata_set_private(pdata, fme);
> + mutex_unlock(&pdata->lock);
> +
> + return 0;
> +}
> +
> +static void fme_dev_destroy(struct platform_device *pdev)
> +{
> + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> + struct dfl_fme *fme;
> +
> + mutex_lock(&pdata->lock);
> + fme = dfl_fpga_pdata_get_private(pdata);
> + dfl_fpga_pdata_set_private(pdata, NULL);
> + mutex_unlock(&pdata->lock);
> +}
> +
> static const struct file_operations fme_fops = {
> .owner = THIS_MODULE,
> .open = fme_open,
> @@ -198,10 +232,14 @@ static int fme_probe(struct platform_device *pdev)
> {
> int ret;
>
> - ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs);
> + ret = fme_dev_init(pdev);
> if (ret)
> goto exit;
>
> + ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs);
> + if (ret)
> + goto dev_destroy;
> +
> ret = dfl_fpga_dev_ops_register(pdev, &fme_fops, THIS_MODULE);
> if (ret)
> goto feature_uinit;
> @@ -210,6 +248,8 @@ static int fme_probe(struct platform_device *pdev)
>
> feature_uinit:
> dfl_fpga_dev_feature_uinit(pdev);
> +dev_destroy:
> + fme_dev_destroy(pdev);
> exit:
> return ret;
> }
> @@ -218,6 +258,7 @@ static int fme_remove(struct platform_device *pdev)
> {
> dfl_fpga_dev_ops_unregister(pdev);
> dfl_fpga_dev_feature_uinit(pdev);
> + fme_dev_destroy(pdev);
>
> return 0;
> }
> diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c
> new file mode 100644
> index 0000000..5939a5c
> --- /dev/null
> +++ b/drivers/fpga/dfl-fme-pr.c
> @@ -0,0 +1,474 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Driver for FPGA Management Engine (FME) Partial Reconfiguration
> + *
> + * Copyright (C) 2017-2018 Intel Corporation, Inc.
> + *
> + * Authors:
> + * Kang Luwei <luwei.kang@intel.com>
> + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> + * Wu Hao <hao.wu@intel.com>
> + * Joseph Grecco <joe.grecco@intel.com>
> + * Enno Luebbers <enno.luebbers@intel.com>
> + * Tim Whisonant <tim.whisonant@intel.com>
> + * Ananda Ravuri <ananda.ravuri@intel.com>
> + * Christopher Rauer <christopher.rauer@intel.com>
> + * Henry Mitchel <henry.mitchel@intel.com>
> + */
> +
> +#include <linux/types.h>
> +#include <linux/device.h>
> +#include <linux/vmalloc.h>
> +#include <linux/uaccess.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/fpga/fpga-bridge.h>
> +#include <linux/fpga/fpga-region.h>
> +#include <linux/fpga-dfl.h>
> +
> +#include "dfl.h"
> +#include "dfl-fme.h"
> +#include "dfl-fme-pr.h"
> +
> +static struct dfl_fme_region *
> +dfl_fme_region_find_by_port_id(struct dfl_fme *fme, int port_id)
> +{
> + struct dfl_fme_region *fme_region;
> +
> + list_for_each_entry(fme_region, &fme->region_list, node)
> + if (fme_region->port_id == port_id)
> + return fme_region;
> +
> + return NULL;
> +}
> +
> +static int dfl_fme_region_match(struct device *dev, const void *data)
> +{
> + return dev->parent == data;
> +}
> +
> +static struct fpga_region *dfl_fme_region_find(struct dfl_fme *fme, int port_id)
> +{
> + struct dfl_fme_region *fme_region;
> + struct fpga_region *region;
> +
> + fme_region = dfl_fme_region_find_by_port_id(fme, port_id);
> + if (!fme_region)
> + return NULL;
> +
> + region = fpga_region_class_find(NULL, &fme_region->region->dev,
> + dfl_fme_region_match);
> + if (!region)
> + return NULL;
> +
> + return region;
> +}
> +
> +static int fme_pr(struct platform_device *pdev, unsigned long arg)
> +{
> + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> + void __user *argp = (void __user *)arg;
> + struct dfl_fpga_fme_port_pr port_pr;
> + struct fpga_image_info *info;
> + struct fpga_region *region;
> + void __iomem *fme_hdr;
> + struct dfl_fme *fme;
> + unsigned long minsz;
> + void *buf = NULL;
> + int ret = 0;
> + u64 v;
> +
> + minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address);
> +
> + if (copy_from_user(&port_pr, argp, minsz))
> + return -EFAULT;
> +
> + if (port_pr.argsz < minsz || port_pr.flags)
> + return -EINVAL;
> +
> + if (!IS_ALIGNED(port_pr.buffer_size, 4))
> + return -EINVAL;
> +
> + /* get fme header region */
> + fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
> + FME_FEATURE_ID_HEADER);
> +
> + /* check port id */
> + v = readq(fme_hdr + FME_HDR_CAP);
> + if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) {
> + dev_dbg(&pdev->dev, "port number more than maximum\n");
> + return -EINVAL;
> + }
> +
> + if (!access_ok(VERIFY_READ,
> + (void __user *)(unsigned long)port_pr.buffer_address,
> + port_pr.buffer_size))
> + return -EFAULT;
> +
> + buf = vmalloc(port_pr.buffer_size);
> + if (!buf)
> + return -ENOMEM;
> +
> + if (copy_from_user(buf,
> + (void __user *)(unsigned long)port_pr.buffer_address,
> + port_pr.buffer_size)) {
> + ret = -EFAULT;
> + goto free_exit;
> + }
> +
> + /* prepare fpga_image_info for PR */
> + info = fpga_image_info_alloc(&pdev->dev);
> + if (!info) {
> + ret = -ENOMEM;
> + goto free_exit;
> + }
> +
> + info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
> +
> + mutex_lock(&pdata->lock);
> + fme = dfl_fpga_pdata_get_private(pdata);
> + /* fme device has been unregistered. */
> + if (!fme) {
> + ret = -EINVAL;
> + goto unlock_exit;
> + }
> +
> + region = dfl_fme_region_find(fme, port_pr.port_id);
> + if (!region) {
> + ret = -EINVAL;
> + goto unlock_exit;
> + }
> +
> + fpga_image_info_free(region->info);
> +
> + info->buf = buf;
> + info->count = port_pr.buffer_size;
> + info->region_id = port_pr.port_id;
> + region->info = info;
> +
> + ret = fpga_region_program_fpga(region);
> +
> + if (region->get_bridges)
> + fpga_bridges_put(®ion->bridge_list);
I'm wondering if this should not be done as part of
fpga_region_program_fpga() (It's not at the moment).
Alan, am I missing something obvious? :)
> +
> + put_device(®ion->dev);
> +unlock_exit:
> + mutex_unlock(&pdata->lock);
> +free_exit:
> + vfree(buf);
> + if (copy_to_user((void __user *)arg, &port_pr, minsz))
> + return -EFAULT;
> +
> + return ret;
> +}
> +
> +/**
> + * dfl_fme_create_mgr - create fpga mgr platform device as child device
> + *
> + * @pdata: fme platform_device's pdata
> + *
> + * Return: mgr platform device if successful, and error code otherwise.
> + */
> +static struct platform_device *
> +dfl_fme_create_mgr(struct dfl_feature_platform_data *pdata,
> + struct dfl_feature *feature)
> +{
> + struct platform_device *mgr, *fme = pdata->dev;
> + struct dfl_fme_mgr_pdata mgr_pdata;
> + int ret = -ENOMEM;
> +
> + if (!feature->ioaddr)
> + return ERR_PTR(-ENODEV);
> +
> + mgr_pdata.ioaddr = feature->ioaddr;
> +
> + /*
> + * Each FME has only one fpga-mgr, so allocate platform device using
> + * the same FME platform device id.
> + */
> + mgr = platform_device_alloc(DFL_FPGA_FME_MGR, fme->id);
> + if (!mgr)
> + return ERR_PTR(ret);
> +
> + mgr->dev.parent = &fme->dev;
> +
> + ret = platform_device_add_data(mgr, &mgr_pdata, sizeof(mgr_pdata));
> + if (ret)
> + goto create_mgr_err;
> +
> + ret = platform_device_add(mgr);
> + if (ret)
> + goto create_mgr_err;
> +
> + return mgr;
> +
> +create_mgr_err:
> + platform_device_put(mgr);
> + return ERR_PTR(ret);
> +}
> +
> +/**
> + * dfl_fme_destroy_mgr - destroy fpga mgr platform device
> + * @pdata: fme platform device's pdata
> + */
> +static void dfl_fme_destroy_mgr(struct dfl_feature_platform_data *pdata)
> +{
> + struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
> +
> + platform_device_unregister(priv->mgr);
> +}
> +
> +/**
> + * dfl_fme_create_bridge - create fme fpga bridge platform device as child
> + *
> + * @pdata: fme platform device's pdata
> + * @port_id: port id for the bridge to be created.
> + *
> + * Return: bridge platform device if successful, and error code otherwise.
> + */
> +static struct dfl_fme_bridge *
> +dfl_fme_create_bridge(struct dfl_feature_platform_data *pdata, int port_id)
> +{
> + struct device *dev = &pdata->dev->dev;
> + struct dfl_fme_br_pdata br_pdata;
> + struct dfl_fme_bridge *fme_br;
> + int ret = -ENOMEM;
> +
> + fme_br = devm_kzalloc(dev, sizeof(*fme_br), GFP_KERNEL);
> + if (!fme_br)
> + return ERR_PTR(ret);
> +
> + br_pdata.cdev = pdata->dfl_cdev;
> + br_pdata.port_id = port_id;
> +
> + fme_br->br = platform_device_alloc(DFL_FPGA_FME_BRIDGE,
> + PLATFORM_DEVID_AUTO);
> + if (!fme_br->br)
> + return ERR_PTR(ret);
> +
> + fme_br->br->dev.parent = dev;
> +
> + ret = platform_device_add_data(fme_br->br, &br_pdata, sizeof(br_pdata));
> + if (ret)
> + goto create_br_err;
> +
> + ret = platform_device_add(fme_br->br);
> + if (ret)
> + goto create_br_err;
> +
> + return fme_br;
> +
> +create_br_err:
> + platform_device_put(fme_br->br);
> + return ERR_PTR(ret);
> +}
> +
> +/**
> + * dfl_fme_destroy_bridge - destroy fpga bridge platform device
> + * @fme_br: fme bridge to destroy
> + */
> +static void dfl_fme_destroy_bridge(struct dfl_fme_bridge *fme_br)
> +{
> + platform_device_unregister(fme_br->br);
> +}
> +
> +/**
> + * dfl_fme_destroy_bridge - destroy all fpga bridge platform device
> + * @pdata: fme platform device's pdata
> + */
> +static void dfl_fme_destroy_bridges(struct dfl_feature_platform_data *pdata)
> +{
> + struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
> + struct dfl_fme_bridge *fbridge, *tmp;
> +
> + list_for_each_entry_safe(fbridge, tmp, &priv->bridge_list, node) {
> + list_del(&fbridge->node);
> + dfl_fme_destroy_bridge(fbridge);
> + }
> +}
> +
> +/**
> + * dfl_fme_create_region - create fpga region platform device as child
> + *
> + * @pdata: fme platform device's pdata
> + * @mgr: mgr platform device needed for region
> + * @br: br platform device needed for region
> + * @port_id: port id
> + *
> + * Return: fme region if successful, and error code otherwise.
> + */
> +static struct dfl_fme_region *
> +dfl_fme_create_region(struct dfl_feature_platform_data *pdata,
> + struct platform_device *mgr,
> + struct platform_device *br, int port_id)
> +{
> + struct dfl_fme_region_pdata region_pdata;
> + struct device *dev = &pdata->dev->dev;
> + struct dfl_fme_region *fme_region;
> + int ret = -ENOMEM;
> +
> + fme_region = devm_kzalloc(dev, sizeof(*fme_region), GFP_KERNEL);
> + if (!fme_region)
> + return ERR_PTR(ret);
> +
> + region_pdata.mgr = mgr;
> + region_pdata.br = br;
> +
> + /*
> + * Each FPGA device may have more than one port, so allocate platform
> + * device using the same port platform device id.
> + */
> + fme_region->region = platform_device_alloc(DFL_FPGA_FME_REGION, br->id);
> + if (!fme_region->region)
> + return ERR_PTR(ret);
> +
> + fme_region->region->dev.parent = dev;
> +
> + ret = platform_device_add_data(fme_region->region, ®ion_pdata,
> + sizeof(region_pdata));
> + if (ret)
> + goto create_region_err;
> +
> + ret = platform_device_add(fme_region->region);
> + if (ret)
> + goto create_region_err;
> +
> + fme_region->port_id = port_id;
> +
> + return fme_region;
> +
> +create_region_err:
> + platform_device_put(fme_region->region);
> + return ERR_PTR(ret);
> +}
> +
> +/**
> + * dfl_fme_destroy_region - destroy fme region
> + * @fme_region: fme region to destroy
> + */
> +static void dfl_fme_destroy_region(struct dfl_fme_region *fme_region)
> +{
> + platform_device_unregister(fme_region->region);
> +}
> +
> +/**
> + * dfl_fme_destroy_regions - destroy all fme regions
> + * @pdata: fme platform device's pdata
> + */
> +static void dfl_fme_destroy_regions(struct dfl_feature_platform_data *pdata)
> +{
> + struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
> + struct dfl_fme_region *fme_region, *tmp;
> +
> + list_for_each_entry_safe(fme_region, tmp, &priv->region_list, node) {
> + list_del(&fme_region->node);
> + dfl_fme_destroy_region(fme_region);
> + }
> +}
> +
> +static int pr_mgmt_init(struct platform_device *pdev,
> + struct dfl_feature *feature)
> +{
> + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> + struct dfl_fme_region *fme_region;
> + struct dfl_fme_bridge *fme_br;
> + struct platform_device *mgr;
> + struct dfl_fme *priv;
> + void __iomem *fme_hdr;
> + int ret = -ENODEV, i = 0;
> + u64 fme_cap, port_offset;
> +
> + fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
> + FME_FEATURE_ID_HEADER);
> +
> + mutex_lock(&pdata->lock);
> + priv = dfl_fpga_pdata_get_private(pdata);
> +
> + /* Initialize the region and bridge sub device list */
> + INIT_LIST_HEAD(&priv->region_list);
> + INIT_LIST_HEAD(&priv->bridge_list);
> +
> + /* Create fpga mgr platform device */
> + mgr = dfl_fme_create_mgr(pdata, feature);
> + if (IS_ERR(mgr)) {
> + dev_err(&pdev->dev, "fail to create fpga mgr pdev\n");
> + goto unlock;
> + }
> +
> + priv->mgr = mgr;
> +
> + /* Read capability register to check number of regions and bridges */
> + fme_cap = readq(fme_hdr + FME_HDR_CAP);
> + for (; i < FIELD_GET(FME_CAP_NUM_PORTS, fme_cap); i++) {
> + port_offset = readq(fme_hdr + FME_HDR_PORT_OFST(i));
> + if (!(port_offset & FME_PORT_OFST_IMP))
> + continue;
> +
> + /* Create bridge for each port */
> + fme_br = dfl_fme_create_bridge(pdata, i);
> + if (IS_ERR(fme_br)) {
> + ret = PTR_ERR(fme_br);
> + goto destroy_region;
> + }
> +
> + list_add(&fme_br->node, &priv->bridge_list);
> +
> + /* Create region for each port */
> + fme_region = dfl_fme_create_region(pdata, mgr,
> + fme_br->br, i);
> + if (!fme_region) {
> + ret = PTR_ERR(fme_region);
> + goto destroy_region;
> + }
> +
> + list_add(&fme_region->node, &priv->region_list);
> + }
> + mutex_unlock(&pdata->lock);
> +
> + return 0;
> +
> +destroy_region:
> + dfl_fme_destroy_regions(pdata);
> + dfl_fme_destroy_bridges(pdata);
> + dfl_fme_destroy_mgr(pdata);
> +unlock:
> + mutex_unlock(&pdata->lock);
> + return ret;
> +}
> +
> +static void pr_mgmt_uinit(struct platform_device *pdev,
> + struct dfl_feature *feature)
> +{
> + struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> + struct dfl_fme *priv;
> +
> + mutex_lock(&pdata->lock);
> + priv = dfl_fpga_pdata_get_private(pdata);
> +
> + dfl_fme_destroy_regions(pdata);
> + dfl_fme_destroy_bridges(pdata);
> + dfl_fme_destroy_mgr(pdata);
> + mutex_unlock(&pdata->lock);
> +}
> +
> +static long fme_pr_ioctl(struct platform_device *pdev,
> + struct dfl_feature *feature,
> + unsigned int cmd, unsigned long arg)
> +{
> + long ret;
> +
> + switch (cmd) {
> + case DFL_FPGA_FME_PORT_PR:
> + ret = fme_pr(pdev, arg);
> + break;
> + default:
> + ret = -ENODEV;
> + }
> +
> + return ret;
> +}
> +
> +const struct dfl_feature_ops pr_mgmt_ops = {
> + .init = pr_mgmt_init,
> + .uinit = pr_mgmt_uinit,
> + .ioctl = fme_pr_ioctl,
> +};
> diff --git a/drivers/fpga/dfl-fme-pr.h b/drivers/fpga/dfl-fme-pr.h
> new file mode 100644
> index 0000000..096a699
> --- /dev/null
> +++ b/drivers/fpga/dfl-fme-pr.h
> @@ -0,0 +1,84 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
> + *
> + * Copyright (C) 2017-2018 Intel Corporation, Inc.
> + *
> + * Authors:
> + * Kang Luwei <luwei.kang@intel.com>
> + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> + * Wu Hao <hao.wu@intel.com>
> + * Joseph Grecco <joe.grecco@intel.com>
> + * Enno Luebbers <enno.luebbers@intel.com>
> + * Tim Whisonant <tim.whisonant@intel.com>
> + * Ananda Ravuri <ananda.ravuri@intel.com>
> + * Henry Mitchel <henry.mitchel@intel.com>
> + */
> +
> +#ifndef __DFL_FME_PR_H
> +#define __DFL_FME_PR_H
> +
> +#include <linux/platform_device.h>
> +
> +/**
> + * struct dfl_fme_region - FME fpga region data structure
> + *
> + * @region: platform device of the FPGA region.
> + * @node: used to link fme_region to a list.
> + * @port_id: indicate which port this region connected to.
> + */
> +struct dfl_fme_region {
> + struct platform_device *region;
> + struct list_head node;
> + int port_id;
> +};
> +
> +/**
> + * struct dfl_fme_region_pdata - platform data for FME region platform device.
> + *
> + * @mgr: platform device of the FPGA manager.
> + * @br: platform device of the FPGA bridge.
> + * @region_id: region id (same as port_id).
> + */
> +struct dfl_fme_region_pdata {
> + struct platform_device *mgr;
> + struct platform_device *br;
> + int region_id;
> +};
> +
> +/**
> + * struct dfl_fme_bridge - FME fpga bridge data structure
> + *
> + * @br: platform device of the FPGA bridge.
> + * @node: used to link fme_bridge to a list.
> + */
> +struct dfl_fme_bridge {
> + struct platform_device *br;
> + struct list_head node;
> +};
> +
> +/**
> + * struct dfl_fme_bridge_pdata - platform data for FME bridge platform device.
> + *
> + * @cdev: container device.
> + * @port_id: port id.
> + */
> +struct dfl_fme_br_pdata {
> + struct dfl_fpga_cdev *cdev;
> + int port_id;
> +};
> +
> +/**
> + * struct dfl_fme_mgr_pdata - platform data for FME manager platform device.
> + *
> + * @ioaddr: mapped io address for FME manager platform device.
> + */
> +struct dfl_fme_mgr_pdata {
> + void __iomem *ioaddr;
> +};
> +
> +#define DFL_FPGA_FME_MGR "dfl-fme-mgr"
> +#define DFL_FPGA_FME_BRIDGE "dfl-fme-bridge"
> +#define DFL_FPGA_FME_REGION "dfl-fme-region"
> +
> +#endif /* __DFL_FME_PR_H */
> diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl-fme.h
> new file mode 100644
> index 0000000..ac6d61a
> --- /dev/null
> +++ b/drivers/fpga/dfl-fme.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Header file for FPGA Management Engine (FME) Driver
> + *
> + * Copyright (C) 2017-2018 Intel Corporation, Inc.
> + *
> + * Authors:
> + * Kang Luwei <luwei.kang@intel.com>
> + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> + * Wu Hao <hao.wu@intel.com>
> + * Joseph Grecco <joe.grecco@intel.com>
> + * Enno Luebbers <enno.luebbers@intel.com>
> + * Tim Whisonant <tim.whisonant@intel.com>
> + * Ananda Ravuri <ananda.ravuri@intel.com>
> + * Henry Mitchel <henry.mitchel@intel.com>
> + */
> +
> +#ifndef __DFL_FME_H
> +#define __DFL_FME_H
> +
> +/**
> + * struct dfl_fme - dfl fme private data
> + *
> + * @mgr: FME's FPGA manager platform device.
> + * @region_list: link list of FME's FPGA regions.
> + * @bridge_list: link list of FME's FPGA bridges.
> + * @pdata: fme platform device's pdata.
> + */
> +struct dfl_fme {
> + struct platform_device *mgr;
> + struct list_head region_list;
> + struct list_head bridge_list;
> + struct dfl_feature_platform_data *pdata;
> +};
> +
> +extern const struct dfl_feature_ops pr_mgmt_ops;
> +
> +#endif /* __DFL_FME_H */
> diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h
> index 9ff26cb..9abfc1d 100644
> --- a/include/uapi/linux/fpga-dfl.h
> +++ b/include/uapi/linux/fpga-dfl.h
> @@ -14,6 +14,8 @@
> #ifndef _UAPI_LINUX_FPGA_DFL_H
> #define _UAPI_LINUX_FPGA_DFL_H
>
> +#include <linux/types.h>
> +
> #define DFL_FPGA_API_VERSION 0
>
> /*
> @@ -26,6 +28,7 @@
> #define DFL_FPGA_MAGIC 0xB6
>
> #define DFL_FPGA_BASE 0
> +#define DFL_FME_BASE 0x80
>
> /**
> * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
> @@ -45,4 +48,29 @@
>
> #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
>
> +/* IOCTLs for FME file descriptor */
> +
> +/**
> + * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0,
> + * struct dfl_fpga_fme_port_pr)
> + *
> + * Driver does Partial Reconfiguration based on Port ID and Buffer (Image)
> + * provided by caller.
> + * Return: 0 on success, -errno on failure.
> + * If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected
> + * some errors during PR, under this case, the user can fetch HW error info
> + * from the status of FME's fpga manager.
> + */
> +
> +struct dfl_fpga_fme_port_pr {
> + /* Input */
> + __u32 argsz; /* Structure length */
> + __u32 flags; /* Zero for now */
> + __u32 port_id;
> + __u32 buffer_size;
> + __u64 buffer_address; /* Userspace address to the buffer for PR */
> +};
> +
> +#define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0)
> +
> #endif /* _UAPI_LINUX_FPGA_DFL_H */
> --
> 1.8.3.1
>
Thanks,
Moritz
^ permalink raw reply
* Re: [PATCH v6 19/29] fpga: dfl: fme-mgr: add compat_id support
From: Moritz Fischer @ 2018-06-13 20:08 UTC (permalink / raw)
To: Wu Hao
Cc: atull, mdf, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang
In-Reply-To: <1528798243-2029-20-git-send-email-hao.wu@intel.com>
On Tue, Jun 12, 2018 at 06:10:33PM +0800, Wu Hao wrote:
> This patch adds compat_id support to fme manager driver, it
> reads the ID from the hardware register. And it could be used
> for compatibility check before partial reconfiguration.
>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> v6: add Acked-by from Alan.
> ---
> drivers/fpga/dfl-fme-mgr.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c
> index be0060a..691761f 100644
> --- a/drivers/fpga/dfl-fme-mgr.c
> +++ b/drivers/fpga/dfl-fme-mgr.c
> @@ -272,9 +272,17 @@ static u64 fme_mgr_status(struct fpga_manager *mgr)
> .status = fme_mgr_status,
> };
>
> +static void fme_mgr_get_compat_id(void __iomem *fme_pr,
> + struct fpga_compat_id *id)
> +{
> + id->id_l = readq(fme_pr + FME_PR_INTFC_ID_L);
> + id->id_h = readq(fme_pr + FME_PR_INTFC_ID_H);
> +}
> +
> static int fme_mgr_probe(struct platform_device *pdev)
> {
> struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);
> + struct fpga_compat_id *compat_id;
> struct device *dev = &pdev->dev;
> struct fme_mgr_priv *priv;
> struct fpga_manager *mgr;
> @@ -295,11 +303,18 @@ static int fme_mgr_probe(struct platform_device *pdev)
> return PTR_ERR(priv->ioaddr);
> }
>
> + compat_id = devm_kzalloc(dev, sizeof(*compat_id), GFP_KERNEL);
> + if (!compat_id)
> + return -ENOMEM;
> +
> + fme_mgr_get_compat_id(priv->ioaddr, compat_id);
> +
> mgr = fpga_mgr_create(dev, "DFL FME FPGA Manager",
> &fme_mgr_ops, priv);
> if (!mgr)
> return -ENOMEM;
>
> + mgr->compat_id = compat_id;
> platform_set_drvdata(pdev, mgr);
>
> ret = fpga_mgr_register(mgr);
> --
> 1.8.3.1
>
Thanks,
Moritz
^ permalink raw reply
* Re: [PATCH v6 12/29] fpga: add FPGA DFL PCIe device driver
From: Wu Hao @ 2018-06-13 16:34 UTC (permalink / raw)
To: Moritz Fischer
Cc: atull, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang, Tim Whisonant, Enno Luebbers, Shiva Rao,
Christopher Rauer, Xiao Guangrong
In-Reply-To: <20180613135420.GB3866@archbook>
On Wed, Jun 13, 2018 at 06:54:20AM -0700, Moritz Fischer wrote:
> On Tue, Jun 12, 2018 at 06:10:26PM +0800, Wu Hao wrote:
> > From: Zhang Yi <yi.z.zhang@intel.com>
> >
> > This patch implements the basic framework of the driver for FPGA PCIe
> > device which implements the Device Feature List (DFL) in its MMIO space.
> > This driver is verified on Intel(R) PCIe based FPGA DFL devices, including
> > both integrated (e.g Intel Server Platform with In-package FPGA) and
> > discrete (e.g Intel FPGA PCIe Acceleration Cards) solutions.
> >
> > Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
> > Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
> > Signed-off-by: Shiva Rao <shiva.rao@intel.com>
> > Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
> > Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
> > Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> > Signed-off-by: Wu Hao <hao.wu@intel.com>
> > Acked-by: Alan Tull <atull@kernel.org>
> > Acked-by: Moritz Fischer <mdf@kernel.org>
> > ---
> > v2: move the code to drivers/fpga folder as suggested by Alan Tull.
> > switch to GPLv2 license.
> > fix comments from Moritz Fischer.
> > v3: switch to pci_set_dma_mask/consistent_dma_mask() function.
> > remove pci_save_state() in probe function.
> > rename driver to INTEL_FPGA_DFL_PCI and intel-dfl-pci.c to indicate
> > this driver supports Intel FPGA PCI devices which implement DFL.
> > improve Kconfig description for INTEL_FPGA_DFL_PCI
> > v4: rename to FPGA_DFL_PCI (dfl-pci.c) for better reuse.
> > fix SPDX license issue.
> > v5: use module_pci_driver() instead.
> > add Acked-by from Alan and Moritz.
> > v6: rebase and unify naming in Kconfig
> > ---
> > drivers/fpga/Kconfig | 15 +++++++
> > drivers/fpga/Makefile | 3 ++
> > drivers/fpga/dfl-pci.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 132 insertions(+)
> > create mode 100644 drivers/fpga/dfl-pci.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index 4052532..5faab48 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -146,4 +146,19 @@ config FPGA_DFL
> > Gate Array (FPGA) solutions which implement Device Feature List.
> > It provides enumeration APIs, and feature device infrastructure.
> >
> > +config FPGA_DFL_PCI
> > + tristate "FPGA DFL PCIe Device Driver"
> > + depends on PCI && FPGA_DFL
> > + help
> > + Select this option to enable PCIe driver for PCIe based
> > + Field-Programmable Gate Array (FPGA) solutions which implemented
> > + the Device Feature List (DFL). This driver provides interfaces
> > + for userspace applications to configure, enumerate, open and access
> > + FPGA accelerators on the FPGA DFL devices, enables system level
> > + management functions such as FPGA partial reconfiguration, power
> > + management, and virtualization with DFL framework and DFL feature
> > + device drivers.
> > +
> > + To compile this as a module, choose M here.
> > +
> > endif # FPGA
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > index 7a7a117..02e0253 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -31,3 +31,6 @@ obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
> >
> > # FPGA Device Feature List Support
> > obj-$(CONFIG_FPGA_DFL) += dfl.o
> > +
> > +# Drivers for FPGAs which implement DFL
> > +obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> > new file mode 100644
> > index 0000000..5824c5e
> > --- /dev/null
> > +++ b/drivers/fpga/dfl-pci.c
> > @@ -0,0 +1,114 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Driver for FPGA Device Feature List (DFL) PCIe device
> > + *
> > + * Copyright (C) 2017-2018 Intel Corporation, Inc.
> > + *
> > + * Authors:
> > + * Zhang Yi <Yi.Z.Zhang@intel.com>
> > + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> > + * Joseph Grecco <joe.grecco@intel.com>
> > + * Enno Luebbers <enno.luebbers@intel.com>
> > + * Tim Whisonant <tim.whisonant@intel.com>
> > + * Ananda Ravuri <ananda.ravuri@intel.com>
> > + * Henry Mitchel <henry.mitchel@intel.com>
> > + */
> > +
> > +#include <linux/pci.h>
> > +#include <linux/types.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/stddef.h>
> > +#include <linux/errno.h>
> > +#include <linux/aer.h>
> > +
> > +#define DRV_VERSION "0.8"
> > +#define DRV_NAME "dfl-pci"
> > +
> > +/* PCI Device ID */
> > +#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
> > +#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
> > +#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
> > +/* VF Device */
> > +#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
> > +#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
> > +#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
> > +
> > +static struct pci_device_id cci_pcie_id_tbl[] = {
> > + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
> > + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
> > + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
> > + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
> > + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
> > + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
> > + {0,}
> > +};
> > +MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
> > +
> > +static
> > +int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
> > +{
> > + int ret;
> > +
> > + ret = pci_enable_device(pcidev);
>
> Any reason we cannot use pcim_enable_device() here?
Hi Moritz
Thanks for the comments, pcim_enable_device() saves code for sure, will switch
to it in the next version.
Thanks
Hao
^ permalink raw reply
* Re: [PATCH 0/6 v1 resend] statfs: handle mount propagation
From: Christian Brauner @ 2018-06-13 15:07 UTC (permalink / raw)
To: Greg KH
Cc: linux-kernel, linux-fsdevel, torvalds, tglx, kstewart,
pombredanne, linux-api, ebiederm, seth.forshee, viro
In-Reply-To: <20180613142454.GA1845@kroah.com>
On Wed, Jun 13, 2018 at 04:24:54PM +0200, Greg KH wrote:
> On Wed, Jun 13, 2018 at 04:06:25PM +0200, Christian Brauner wrote:
> > On Fri, May 25, 2018 at 02:48:19PM +0200, Christian Brauner wrote:
> > > From: Christian Brauner <christian.brauner@ubuntu.com>
> > >
> > > Hey,
> > >
> > > This is v1 of this patchset. All changes from v0 to v1 are non-functional.
> > > Specifically, the commit messages and justification have been extended as
> > > requested by Linus and Al.
> >
> > Hey everyone,
> >
> > Just a ping whether the requested changes have made this series suitable
> > for inclusion. Would be excellent if someone could do another review. :)
>
> It's the middle of the merge window, no new code gets accepted right
> now, so just wait until next week at the _earliest_ before worrying
Ok, sorry. It was just that this was sent out before well over a month
ago and I was just worried that it had been overlooked.
Thanks!
Christian
> about someone reviewing this.
>
> thanks,
>
> greg k-h
^ permalink raw reply
* Re: [PATCH v6 05/29] fpga: region: add compat_id support
From: Moritz Fischer @ 2018-06-13 14:44 UTC (permalink / raw)
To: Wu Hao
Cc: atull, mdf, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang
In-Reply-To: <1528798243-2029-6-git-send-email-hao.wu@intel.com>
On Tue, Jun 12, 2018 at 06:10:19PM +0800, Wu Hao wrote:
> This patch introduces a compat_id pointer member and sysfs interface
> for each fpga region, similar as compat_id for fpga manager, it allows
> applications to read the per region compat_id for compatibility
> checking before other actions on this fpga-region (e.g PR).
>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> v5: use pointer for compat_id as it's optional to implement.
> v6: add Acked-by from Alan.
> ---
> Documentation/ABI/testing/sysfs-class-fpga-region | 9 +++++++++
> drivers/fpga/fpga-region.c | 22 ++++++++++++++++++++++
> include/linux/fpga/fpga-region.h | 2 ++
> 3 files changed, 33 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-class-fpga-region
>
> diff --git a/Documentation/ABI/testing/sysfs-class-fpga-region b/Documentation/ABI/testing/sysfs-class-fpga-region
> new file mode 100644
> index 0000000..ffdc853
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-class-fpga-region
> @@ -0,0 +1,9 @@
> +What: /sys/class/fpga_region/<region>/compat_id
> +Date: June 2018
> +KernelVersion: 4.18
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: FPGA region id for compatibility check, e.g compatibility
> + of the FPGA reconfiguration hardware and image. This value
> + is defined or calculated by the layer that is creating the
> + FPGA region. This interface returns the compat_id value or
> + just error code -ENOENT in case compat_id is not used.
> diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
> index 6d214d7..0d65220 100644
> --- a/drivers/fpga/fpga-region.c
> +++ b/drivers/fpga/fpga-region.c
> @@ -158,6 +158,27 @@ int fpga_region_program_fpga(struct fpga_region *region)
> }
> EXPORT_SYMBOL_GPL(fpga_region_program_fpga);
>
> +static ssize_t compat_id_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct fpga_region *region = to_fpga_region(dev);
> +
> + if (!region->compat_id)
> + return -ENOENT;
> +
> + return sprintf(buf, "%016llx%016llx\n",
> + (unsigned long long)region->compat_id->id_h,
> + (unsigned long long)region->compat_id->id_l);
> +}
> +
> +static DEVICE_ATTR_RO(compat_id);
> +
> +static struct attribute *fpga_region_attrs[] = {
> + &dev_attr_compat_id.attr,
> + NULL,
> +};
> +ATTRIBUTE_GROUPS(fpga_region);
> +
> /**
> * fpga_region_create - alloc and init a struct fpga_region
> * @dev: device parent
> @@ -258,6 +279,7 @@ static int __init fpga_region_init(void)
> if (IS_ERR(fpga_region_class))
> return PTR_ERR(fpga_region_class);
>
> + fpga_region_class->dev_groups = fpga_region_groups;
> fpga_region_class->dev_release = fpga_region_dev_release;
>
> return 0;
> diff --git a/include/linux/fpga/fpga-region.h b/include/linux/fpga/fpga-region.h
> index d7071cd..0521b7f 100644
> --- a/include/linux/fpga/fpga-region.h
> +++ b/include/linux/fpga/fpga-region.h
> @@ -14,6 +14,7 @@
> * @bridge_list: list of FPGA bridges specified in region
> * @mgr: FPGA manager
> * @info: FPGA image info
> + * @compat_id: FPGA region id for compatibility check.
> * @priv: private data
> * @get_bridges: optional function to get bridges to a list
> */
> @@ -23,6 +24,7 @@ struct fpga_region {
> struct list_head bridge_list;
> struct fpga_manager *mgr;
> struct fpga_image_info *info;
> + struct fpga_compat_id *compat_id;
> void *priv;
> int (*get_bridges)(struct fpga_region *region);
> };
> --
> 1.8.3.1
>
Thanks,
Moritz
^ permalink raw reply
* Re: [PATCH 0/6 v1 resend] statfs: handle mount propagation
From: Greg KH @ 2018-06-13 14:24 UTC (permalink / raw)
To: Christian Brauner
Cc: linux-kernel, linux-fsdevel, torvalds, tglx, kstewart,
pombredanne, linux-api, ebiederm, seth.forshee, viro
In-Reply-To: <20180613140625.GA31082@mailbox.org>
On Wed, Jun 13, 2018 at 04:06:25PM +0200, Christian Brauner wrote:
> On Fri, May 25, 2018 at 02:48:19PM +0200, Christian Brauner wrote:
> > From: Christian Brauner <christian.brauner@ubuntu.com>
> >
> > Hey,
> >
> > This is v1 of this patchset. All changes from v0 to v1 are non-functional.
> > Specifically, the commit messages and justification have been extended as
> > requested by Linus and Al.
>
> Hey everyone,
>
> Just a ping whether the requested changes have made this series suitable
> for inclusion. Would be excellent if someone could do another review. :)
It's the middle of the merge window, no new code gets accepted right
now, so just wait until next week at the _earliest_ before worrying
about someone reviewing this.
thanks,
greg k-h
^ permalink raw reply
* Re: [PATCH v6 22/29] fpga: dfl: fme-region: add support for compat_id
From: Moritz Fischer @ 2018-06-13 14:18 UTC (permalink / raw)
To: Wu Hao
Cc: atull, mdf, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang
In-Reply-To: <1528798243-2029-23-git-send-email-hao.wu@intel.com>
On Tue, Jun 12, 2018 at 06:10:36PM +0800, Wu Hao wrote:
> This patch adds compat_id support, it reuses fme manager's
> compat id, as the per region compat id is actually from the
> fme manager's register.
>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> v5: reuse fme manager's compat_id as per region compat_id
> v6: rebase, fix copyright time and add Acked-by from Alan.
> ---
> drivers/fpga/dfl-fme-region.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/fpga/dfl-fme-region.c b/drivers/fpga/dfl-fme-region.c
> index a6e0bde..0b7e19c 100644
> --- a/drivers/fpga/dfl-fme-region.c
> +++ b/drivers/fpga/dfl-fme-region.c
> @@ -45,6 +45,7 @@ static int fme_region_probe(struct platform_device *pdev)
> }
>
> region->priv = pdata;
> + region->compat_id = mgr->compat_id;
> platform_set_drvdata(pdev, region);
>
> ret = fpga_region_register(region);
> --
> 1.8.3.1
>
^ permalink raw reply
* Re: [PATCH v6 14/29] fpga: dfl: add FPGA Management Engine driver basic framework
From: Moritz Fischer @ 2018-06-13 14:13 UTC (permalink / raw)
To: Wu Hao
Cc: atull, mdf, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang, Tim Whisonant, Enno Luebbers, Shiva Rao,
Christopher Rauer, Xiao Guangrong
In-Reply-To: <1528798243-2029-15-git-send-email-hao.wu@intel.com>
On Tue, Jun 12, 2018 at 06:10:28PM +0800, Wu Hao wrote:
> From: Kang Luwei <luwei.kang@intel.com>
>
> The FPGA Management Engine (FME) provides power, thermal management,
> performance counters, partial reconfiguration and other functions. For each
> function, it is packaged into a private feature linked to the FME feature
> device in the 'Device Feature List'. It's a platform device created by
> DFL framework.
>
> This patch adds the basic framework of FME platform driver. It defines
> sub feature drivers to handle the different sub features, including init,
> uinit and ioctl. It also registers the file operations for the device file.
>
> Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
> Signed-off-by: Shiva Rao <shiva.rao@intel.com>
> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
> Signed-off-by: Kang Luwei <luwei.kang@intel.com>
> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> v3: rename driver from intel-fpga-fme to dfl-fme
> rename Kconfig from INTEL_FPGA_FME to FPGA_DFL_FME
> v4: fix SPDX license issue, use dfl-fme as module name
> v5: rebase, due to DFL framework naming changes on functions and data structures.
> fix uinit order in remove function.
> remove else block in fme_ioctl function per suggestion from Alan.
> v6: fix copyright time, rebase and add Acked-by from Alan.
> ---
> drivers/fpga/Kconfig | 10 +++
> drivers/fpga/Makefile | 3 +
> drivers/fpga/dfl-fme-main.c | 158 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 171 insertions(+)
> create mode 100644 drivers/fpga/dfl-fme-main.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 5faab48..45e9220 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -146,6 +146,16 @@ config FPGA_DFL
> Gate Array (FPGA) solutions which implement Device Feature List.
> It provides enumeration APIs, and feature device infrastructure.
>
> +config FPGA_DFL_FME
> + tristate "FPGA DFL FME Driver"
> + depends on FPGA_DFL
> + help
> + The FPGA Management Engine (FME) is a feature device implemented
> + under Device Feature List (DFL) framework. Select this option to
> + enable the platform device driver for FME which implements all
> + FPGA platform level management features. There shall be 1 FME
> + per DFL based FPGA device.
> +
> config FPGA_DFL_PCI
> tristate "FPGA DFL PCIe Device Driver"
> depends on PCI && FPGA_DFL
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 02e0253..db11f34 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -31,6 +31,9 @@ obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
>
> # FPGA Device Feature List Support
> obj-$(CONFIG_FPGA_DFL) += dfl.o
> +obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
> +
> +dfl-fme-objs := dfl-fme-main.o
>
> # Drivers for FPGAs which implement DFL
> obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
> new file mode 100644
> index 0000000..a2ae9b3
> --- /dev/null
> +++ b/drivers/fpga/dfl-fme-main.c
> @@ -0,0 +1,158 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Driver for FPGA Management Engine (FME)
> + *
> + * Copyright (C) 2017-2018 Intel Corporation, Inc.
> + *
> + * Authors:
> + * Kang Luwei <luwei.kang@intel.com>
> + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> + * Joseph Grecco <joe.grecco@intel.com>
> + * Enno Luebbers <enno.luebbers@intel.com>
> + * Tim Whisonant <tim.whisonant@intel.com>
> + * Ananda Ravuri <ananda.ravuri@intel.com>
> + * Henry Mitchel <henry.mitchel@intel.com>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +
> +#include "dfl.h"
> +
> +static int fme_hdr_init(struct platform_device *pdev,
> + struct dfl_feature *feature)
> +{
> + dev_dbg(&pdev->dev, "FME HDR Init.\n");
> +
> + return 0;
> +}
> +
> +static void fme_hdr_uinit(struct platform_device *pdev,
> + struct dfl_feature *feature)
> +{
> + dev_dbg(&pdev->dev, "FME HDR UInit.\n");
> +}
> +
> +static const struct dfl_feature_ops fme_hdr_ops = {
> + .init = fme_hdr_init,
> + .uinit = fme_hdr_uinit,
> +};
> +
> +static struct dfl_feature_driver fme_feature_drvs[] = {
> + {
> + .id = FME_FEATURE_ID_HEADER,
> + .ops = &fme_hdr_ops,
> + },
> + {
> + .ops = NULL,
> + },
> +};
> +
> +static int fme_open(struct inode *inode, struct file *filp)
> +{
> + struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode);
> + struct dfl_feature_platform_data *pdata = dev_get_platdata(&fdev->dev);
> + int ret;
> +
> + if (WARN_ON(!pdata))
> + return -ENODEV;
> +
> + ret = dfl_feature_dev_use_begin(pdata);
> + if (ret)
> + return ret;
> +
> + dev_dbg(&fdev->dev, "Device File Open\n");
> + filp->private_data = pdata;
> +
> + return 0;
> +}
> +
> +static int fme_release(struct inode *inode, struct file *filp)
> +{
> + struct dfl_feature_platform_data *pdata = filp->private_data;
> + struct platform_device *pdev = pdata->dev;
> +
> + dev_dbg(&pdev->dev, "Device File Release\n");
> + dfl_feature_dev_use_end(pdata);
> +
> + return 0;
> +}
> +
> +static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
> +{
> + struct dfl_feature_platform_data *pdata = filp->private_data;
> + struct platform_device *pdev = pdata->dev;
> + struct dfl_feature *f;
> + long ret;
> +
> + dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
> +
> + switch (cmd) {
> + default:
> + /*
> + * Let sub-feature's ioctl function to handle the cmd
> + * Sub-feature's ioctl returns -ENODEV when cmd is not
> + * handled in this sub feature, and returns 0 and other
> + * error code if cmd is handled.
> + */
> + dfl_fpga_dev_for_each_feature(pdata, f) {
> + if (f->ops && f->ops->ioctl) {
> + ret = f->ops->ioctl(pdev, f, cmd, arg);
> + if (ret != -ENODEV)
> + return ret;
> + }
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +static const struct file_operations fme_fops = {
> + .owner = THIS_MODULE,
> + .open = fme_open,
> + .release = fme_release,
> + .unlocked_ioctl = fme_ioctl,
> +};
> +
> +static int fme_probe(struct platform_device *pdev)
> +{
> + int ret;
> +
> + ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs);
> + if (ret)
> + goto exit;
> +
> + ret = dfl_fpga_dev_ops_register(pdev, &fme_fops, THIS_MODULE);
> + if (ret)
> + goto feature_uinit;
> +
> + return 0;
> +
> +feature_uinit:
> + dfl_fpga_dev_feature_uinit(pdev);
> +exit:
> + return ret;
> +}
> +
> +static int fme_remove(struct platform_device *pdev)
> +{
> + dfl_fpga_dev_ops_unregister(pdev);
> + dfl_fpga_dev_feature_uinit(pdev);
> +
> + return 0;
> +}
> +
> +static struct platform_driver fme_driver = {
> + .driver = {
> + .name = DFL_FPGA_FEATURE_DEV_FME,
> + },
> + .probe = fme_probe,
> + .remove = fme_remove,
> +};
> +
> +module_platform_driver(fme_driver);
> +
> +MODULE_DESCRIPTION("FPGA Management Engine driver");
> +MODULE_AUTHOR("Intel Corporation");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:dfl-fme");
> --
> 1.8.3.1
>
Thanks,
Moritz
^ permalink raw reply
* Re: [PATCH 0/6 v1 resend] statfs: handle mount propagation
From: Christian Brauner @ 2018-06-13 14:06 UTC (permalink / raw)
To: linux-kernel, linux-fsdevel
Cc: torvalds, tglx, kstewart, gregkh, pombredanne, linux-api,
ebiederm, seth.forshee, viro
In-Reply-To: <20180525124825.23875-1-christian@brauner.io>
On Fri, May 25, 2018 at 02:48:19PM +0200, Christian Brauner wrote:
> From: Christian Brauner <christian.brauner@ubuntu.com>
>
> Hey,
>
> This is v1 of this patchset. All changes from v0 to v1 are non-functional.
> Specifically, the commit messages and justification have been extended as
> requested by Linus and Al.
Hey everyone,
Just a ping whether the requested changes have made this series suitable
for inclusion. Would be excellent if someone could do another review. :)
Thanks!
Christian
>
> This little series does the following:
>
> - unify the definition of constants in statfs.h and fs.h:
> The definitions for MS_* flags are currently a mixture between hex values
> and bit-shifts. All higher values are already initialized with bit-shifts
> for MS_* constants starting with (1<<16). This patch switches the
> definitions for MS_* constants over to uniformly use bit-shifts and
> alignes the definitions of ST_* flags too.
> Initializing them identically let's userspace easily detect when flags
> indicate the same property but use a different value in doing so.
>
> - extend statfs to handle mount propagation:
> For all cases the only way to do this right now is by parsing
> /proc/<pid>/mountinfo. Yes, it is doable but still it is somewhat costly
> and annoying as e.g. those mount propagation fields are optional.
> 1. prevent propagation from happening:
> From a userspace perspective we often run into the case where we
> simply want to know whether a given mountpoint is MS_SHARED or is
> MS_SLAVE. If it is we remount it as MS_PRIVATE to prevent any
> propagation from happening. We don't care about the peer
> relationship or how the propagation is exactly setup. We only want
> to prevent any propagation from happening.
> These mountpoints might be known in advance so parsing
> /proc/<pid>/mountinfo should not be needed.
> 2. differentiate between MS_SLAVE and MS_SHARED mountpoints:
> Mountpoints that are MS_SLAVE are kept intact and mountpoints that
> are MS_SHARED are made MS_PRIVATE. These mountpoint might be known in
> advance so parsing /proc/<pid>/mountinfo should not be needed.
> 3. retrieve propagation properties when procfs is not mounted:
> When the set of interesting mountpoints is known and /proc is not
> mounted calling statfs() is the only good way to reliably determine
> the propagation property of a mountpoint.
> 4. inspecting file descriptors to mountpoints for propagation
> properties:
> When file descriptors to mountpoints are passed around between
> processes it is useful to have fstatvfs() handle mount propagation
> properties too.
> To this end the flags:
> - ST_UNBINDABLE
> - ST_SHARED
> - ST_PRIVATE
> - ST_SLAVE
> are added. They have the same value as their MS_* counterparts.
>
> - Testing:
> I verified that now userspace can do e.g.
>
> int ret;
> char *s = "/some/path";
> struct statvfs sb;
>
> ret = statvfs(s, &sb);
> if (ret < 0)
> return false;
>
> if (sb.f_flag & ST_SHARED) {
> ret = mount("", s, NULL, MS_SLAVE | MS_REC, NULL);
> if (ret < 0)
> return -1;
> }
>
> Thanks!
> Christian
>
> Christian Brauner (6):
> fs: use << for MS_* flags
> statfs: use << to align with fs header
> statfs: add ST_UNBINDABLE
> statfs: add ST_SHARED
> statfs: add ST_SLAVE
> statfs: add ST_PRIVATE
>
> fs/statfs.c | 16 +++++++++++++++-
> include/linux/statfs.h | 30 +++++++++++++++++-------------
> include/uapi/linux/fs.h | 33 +++++++++++++++++----------------
> 3 files changed, 49 insertions(+), 30 deletions(-)
>
> --
> 2.17.0
>
^ permalink raw reply
* Re: [PATCH v6 12/29] fpga: add FPGA DFL PCIe device driver
From: Moritz Fischer @ 2018-06-13 13:54 UTC (permalink / raw)
To: Wu Hao
Cc: atull, mdf, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang, Tim Whisonant, Enno Luebbers, Shiva Rao,
Christopher Rauer, Xiao Guangrong
In-Reply-To: <1528798243-2029-13-git-send-email-hao.wu@intel.com>
On Tue, Jun 12, 2018 at 06:10:26PM +0800, Wu Hao wrote:
> From: Zhang Yi <yi.z.zhang@intel.com>
>
> This patch implements the basic framework of the driver for FPGA PCIe
> device which implements the Device Feature List (DFL) in its MMIO space.
> This driver is verified on Intel(R) PCIe based FPGA DFL devices, including
> both integrated (e.g Intel Server Platform with In-package FPGA) and
> discrete (e.g Intel FPGA PCIe Acceleration Cards) solutions.
>
> Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
> Signed-off-by: Shiva Rao <shiva.rao@intel.com>
> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
> Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Alan Tull <atull@kernel.org>
> Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> v2: move the code to drivers/fpga folder as suggested by Alan Tull.
> switch to GPLv2 license.
> fix comments from Moritz Fischer.
> v3: switch to pci_set_dma_mask/consistent_dma_mask() function.
> remove pci_save_state() in probe function.
> rename driver to INTEL_FPGA_DFL_PCI and intel-dfl-pci.c to indicate
> this driver supports Intel FPGA PCI devices which implement DFL.
> improve Kconfig description for INTEL_FPGA_DFL_PCI
> v4: rename to FPGA_DFL_PCI (dfl-pci.c) for better reuse.
> fix SPDX license issue.
> v5: use module_pci_driver() instead.
> add Acked-by from Alan and Moritz.
> v6: rebase and unify naming in Kconfig
> ---
> drivers/fpga/Kconfig | 15 +++++++
> drivers/fpga/Makefile | 3 ++
> drivers/fpga/dfl-pci.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 132 insertions(+)
> create mode 100644 drivers/fpga/dfl-pci.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 4052532..5faab48 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -146,4 +146,19 @@ config FPGA_DFL
> Gate Array (FPGA) solutions which implement Device Feature List.
> It provides enumeration APIs, and feature device infrastructure.
>
> +config FPGA_DFL_PCI
> + tristate "FPGA DFL PCIe Device Driver"
> + depends on PCI && FPGA_DFL
> + help
> + Select this option to enable PCIe driver for PCIe based
> + Field-Programmable Gate Array (FPGA) solutions which implemented
> + the Device Feature List (DFL). This driver provides interfaces
> + for userspace applications to configure, enumerate, open and access
> + FPGA accelerators on the FPGA DFL devices, enables system level
> + management functions such as FPGA partial reconfiguration, power
> + management, and virtualization with DFL framework and DFL feature
> + device drivers.
> +
> + To compile this as a module, choose M here.
> +
> endif # FPGA
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 7a7a117..02e0253 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -31,3 +31,6 @@ obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
>
> # FPGA Device Feature List Support
> obj-$(CONFIG_FPGA_DFL) += dfl.o
> +
> +# Drivers for FPGAs which implement DFL
> +obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> new file mode 100644
> index 0000000..5824c5e
> --- /dev/null
> +++ b/drivers/fpga/dfl-pci.c
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Driver for FPGA Device Feature List (DFL) PCIe device
> + *
> + * Copyright (C) 2017-2018 Intel Corporation, Inc.
> + *
> + * Authors:
> + * Zhang Yi <Yi.Z.Zhang@intel.com>
> + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> + * Joseph Grecco <joe.grecco@intel.com>
> + * Enno Luebbers <enno.luebbers@intel.com>
> + * Tim Whisonant <tim.whisonant@intel.com>
> + * Ananda Ravuri <ananda.ravuri@intel.com>
> + * Henry Mitchel <henry.mitchel@intel.com>
> + */
> +
> +#include <linux/pci.h>
> +#include <linux/types.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/stddef.h>
> +#include <linux/errno.h>
> +#include <linux/aer.h>
> +
> +#define DRV_VERSION "0.8"
> +#define DRV_NAME "dfl-pci"
> +
> +/* PCI Device ID */
> +#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
> +#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
> +#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
> +/* VF Device */
> +#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
> +#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
> +#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
> +
> +static struct pci_device_id cci_pcie_id_tbl[] = {
> + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
> + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
> + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
> + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
> + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
> + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
> + {0,}
> +};
> +MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
> +
> +static
> +int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
> +{
> + int ret;
> +
> + ret = pci_enable_device(pcidev);
Any reason we cannot use pcim_enable_device() here?
> + if (ret < 0) {
> + dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
> + return ret;
> + }
> +
> + ret = pci_enable_pcie_error_reporting(pcidev);
> + if (ret && ret != -EINVAL)
> + dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);
> +
> + ret = pci_request_regions(pcidev, DRV_NAME);
> + if (ret) {
> + dev_err(&pcidev->dev, "Failed to request regions.\n");
> + goto disable_error_report_exit;
> + }
> +
> + pci_set_master(pcidev);
> +
> + if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
> + ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
> + if (ret)
> + goto release_region_exit;
> + } else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) {
> + ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
> + if (ret)
> + goto release_region_exit;
> + } else {
> + ret = -EIO;
> + dev_err(&pcidev->dev, "No suitable DMA support available.\n");
> + goto release_region_exit;
> + }
> +
> + /* TODO: create and add the platform device per feature list */
> + return 0;
> +
> +release_region_exit:
> + pci_release_regions(pcidev);
> +disable_error_report_exit:
> + pci_disable_pcie_error_reporting(pcidev);
> + pci_disable_device(pcidev);
> + return ret;
> +}
> +
> +static void cci_pci_remove(struct pci_dev *pcidev)
> +{
> + pci_release_regions(pcidev);
> + pci_disable_pcie_error_reporting(pcidev);
> + pci_disable_device(pcidev);
> +}
> +
> +static struct pci_driver cci_pci_driver = {
> + .name = DRV_NAME,
> + .id_table = cci_pcie_id_tbl,
> + .probe = cci_pci_probe,
> + .remove = cci_pci_remove,
> +};
> +
> +module_pci_driver(cci_pci_driver);
> +
> +MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
> +MODULE_AUTHOR("Intel Corporation");
> +MODULE_LICENSE("GPL v2");
> --
> 1.8.3.1
>
Cheers,
Moritz
^ permalink raw reply
* Re: [PATCH v6 29/29] MAINTAINERS: add entry for FPGA DFL drivers
From: Moritz Fischer @ 2018-06-13 13:50 UTC (permalink / raw)
To: Wu Hao
Cc: atull, mdf, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang
In-Reply-To: <1528798243-2029-30-git-send-email-hao.wu@intel.com>
On Tue, Jun 12, 2018 at 06:10:43PM +0800, Wu Hao wrote:
> Add entry for FPGA Device Feature List (DFL) drivers.
>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> MAINTAINERS | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 448957c..98fc5ea 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5619,6 +5619,14 @@ F: drivers/fpga/
> F: include/linux/fpga/
> W: http://www.rocketboards.org
>
> +FPGA DFL DRIVERS
> +M: Wu Hao <hao.wu@intel.com>
> +L: linux-fpga@vger.kernel.org
> +S: Maintained
> +F: Documentation/fpga/dfl.txt
> +F: include/uapi/linux/fpga-dfl.h
> +F: drivers/fpga/dfl*
> +
> FPU EMULATOR
> M: Bill Metzenthen <billm@melbpc.org.au>
> W: http://floatingpoint.sourceforge.net/emulator/index.html
> --
> 1.8.3.1
>
Thanks,
Moritz
^ permalink raw reply
* Re: [PATCH] mm/madvise: allow MADV_DONTNEED to free memory that is MLOCK_ONFAULT
From: Michal Hocko @ 2018-06-13 9:13 UTC (permalink / raw)
To: Jason Baron
Cc: akpm, linux-kernel, linux-mm, Vlastimil Babka, Joonsoo Kim,
Mel Gorman, Kirill A. Shutemov, linux-api, emunson
In-Reply-To: <5a9398f4-453c-5cb5-6bbc-f20c3affc96a@akamai.com>
On Tue 12-06-18 10:11:33, Jason Baron wrote:
[...]
> Ok, I share the concern that there is a chance that userspace is relying
> on MADV_DONTNEED not free'ing locked memory. In that case, what if we
> introduce a MADV_DONTNEED_FORCE, which does everything that
> MADV_DONTNEED currently does but in addition will also free mlock areas.
What about other types of vmas that are not allowed to MADV_DONTNEED?
_FORCE suggests that the user of the API know what he is doing so why
shouldn't we allow unmapping hugetlb pages or special PFNMAPS? Or do we
want to add MADV_DONTNEED_FORCE_FOR_REAL when somebody comes with
another usecase?
I agree with Vlastimil that adding new madvise mode for niche case
sounds like a bad idea so we should better be sure that a new flag has
a reasonable semantic. Just allow mlocked pages is more of a tweak than
a proper semantic. So making it force for real requires to analyze what
that would mean for other vmas which are excluded now.
--
Michal Hocko
SUSE Labs
^ permalink raw reply
* Re: [PATCH] mm/madvise: allow MADV_DONTNEED to free memory that is MLOCK_ONFAULT
From: Michal Hocko @ 2018-06-13 8:37 UTC (permalink / raw)
To: Vlastimil Babka
Cc: Jason Baron, akpm, linux-kernel, linux-mm, Joonsoo Kim,
Mel Gorman, Kirill A. Shutemov, linux-api, emunson
In-Reply-To: <5eb9a018-d5ac-5732-04f1-222c343b840a@suse.cz>
On Wed 13-06-18 09:51:23, Vlastimil Babka wrote:
> On 06/13/2018 09:15 AM, Michal Hocko wrote:
> > On Wed 13-06-18 08:32:19, Vlastimil Babka wrote:
[...]
> >> I think more concerning than guaranteeing no later major fault is
> >> possible data loss, e.g. replacing data with zero-filled pages.
> >
> > But MADV_DONTNEED is an explicit call for data loss. Or do I miss your
> > point?
>
> My point is that if somebody is relying on MADV_DONTNEED not affecting
> mlocked pages, the consequences will be unexpected data loss, not just
> extra page faults.
OK, I see your point now. I would consider this an application bug
though. Calling MADV_DONTNEED and wondering that the content is gone is,
ehm, questionable at best. Why would anybody do that in the first place?
Anyway, I think that we cannot change the behavior because of mlockall
semantic as mentioned earlier.
--
Michal Hocko
SUSE Labs
^ permalink raw reply
* Re: [PATCH] mm/madvise: allow MADV_DONTNEED to free memory that is MLOCK_ONFAULT
From: Vlastimil Babka @ 2018-06-13 7:51 UTC (permalink / raw)
To: Michal Hocko
Cc: Jason Baron, akpm, linux-kernel, linux-mm, Joonsoo Kim,
Mel Gorman, Kirill A. Shutemov, linux-api, emunson
In-Reply-To: <20180613071552.GD13364@dhcp22.suse.cz>
On 06/13/2018 09:15 AM, Michal Hocko wrote:
> On Wed 13-06-18 08:32:19, Vlastimil Babka wrote:
>> On 06/12/2018 04:11 PM, Jason Baron wrote:
>>>
>>>
>>> On 06/12/2018 03:46 AM, Michal Hocko wrote:
>>>> On Mon 11-06-18 12:23:58, Jason Baron wrote:
>>>>> On 06/11/2018 11:03 AM, Michal Hocko wrote:
>>>>>> So can we start discussing whether we want to allow MADV_DONTNEED on
>>>>>> mlocked areas and what downsides it might have? Sure it would turn the
>>>>>> strong mlock guarantee to have the whole vma resident but is this
>>>>>> acceptable for something that is an explicit request from the owner of
>>>>>> the memory?
>>>>>>
>>>>>
>>>>> If its being explicity requested by the owner it makes sense to me. I
>>>>> guess there could be a concern about this breaking some userspace that
>>>>> relied on MADV_DONTNEED not freeing locked memory?
>>>>
>>>> Yes, this is always the fear when changing user visible behavior. I can
>>>> imagine that a userspace allocator calling MADV_DONTNEED on free could
>>>> break. The same would apply to MLOCK_ONFAULT/MCL_ONFAULT though. We
>>>> have the new flag much shorter so the probability is smaller but the
>>>> problem is very same. So I _think_ we should treat both the same because
>>>> semantically they are indistinguishable from the MADV_DONTNEED POV. Both
>>>> remove faulted and mlocked pages. Mlock, once applied, should guarantee
>>>> no later major fault and MADV_DONTNEED breaks that obviously.
>>
>> I think more concerning than guaranteeing no later major fault is
>> possible data loss, e.g. replacing data with zero-filled pages.
>
> But MADV_DONTNEED is an explicit call for data loss. Or do I miss your
> point?
My point is that if somebody is relying on MADV_DONTNEED not affecting
mlocked pages, the consequences will be unexpected data loss, not just
extra page faults.
>> The madvise manpage is also quite specific about not allowing
>> MADV_DONTNEED and MADV_FREE for locked pages.
>
> Yeah, but that seems to describe the state of the art rather than
> explain why.
Right, but as it's explicitly described there, it makes it more likely
that somebody is relying on it.
>> So I don't think we should risk changing that for all mlocked pages.
>> Maybe we can risk MCL_ONFAULT, since it's relatively new and has few users?
>
> That is what Jason wanted but I argued that the two are the same from
> MADV_DONTNEED point of view. I do not see how treating them differently
> would be less confusing or error prone. It's new so we can make it
> behave differently is certainly not an argument.
Right. Might be either this inconsistency, or a new flag.
^ permalink raw reply
* Re: [PATCH] mm/madvise: allow MADV_DONTNEED to free memory that is MLOCK_ONFAULT
From: Michal Hocko @ 2018-06-13 7:15 UTC (permalink / raw)
To: Vlastimil Babka
Cc: Jason Baron, akpm, linux-kernel, linux-mm, Joonsoo Kim,
Mel Gorman, Kirill A. Shutemov, linux-api, emunson
In-Reply-To: <0daccb7c-f642-c5ce-ca7a-3b3e69025a1e@suse.cz>
On Wed 13-06-18 08:32:19, Vlastimil Babka wrote:
> On 06/12/2018 04:11 PM, Jason Baron wrote:
> >
> >
> > On 06/12/2018 03:46 AM, Michal Hocko wrote:
> >> On Mon 11-06-18 12:23:58, Jason Baron wrote:
> >>> On 06/11/2018 11:03 AM, Michal Hocko wrote:
> >>>> So can we start discussing whether we want to allow MADV_DONTNEED on
> >>>> mlocked areas and what downsides it might have? Sure it would turn the
> >>>> strong mlock guarantee to have the whole vma resident but is this
> >>>> acceptable for something that is an explicit request from the owner of
> >>>> the memory?
> >>>>
> >>>
> >>> If its being explicity requested by the owner it makes sense to me. I
> >>> guess there could be a concern about this breaking some userspace that
> >>> relied on MADV_DONTNEED not freeing locked memory?
> >>
> >> Yes, this is always the fear when changing user visible behavior. I can
> >> imagine that a userspace allocator calling MADV_DONTNEED on free could
> >> break. The same would apply to MLOCK_ONFAULT/MCL_ONFAULT though. We
> >> have the new flag much shorter so the probability is smaller but the
> >> problem is very same. So I _think_ we should treat both the same because
> >> semantically they are indistinguishable from the MADV_DONTNEED POV. Both
> >> remove faulted and mlocked pages. Mlock, once applied, should guarantee
> >> no later major fault and MADV_DONTNEED breaks that obviously.
>
> I think more concerning than guaranteeing no later major fault is
> possible data loss, e.g. replacing data with zero-filled pages.
But MADV_DONTNEED is an explicit call for data loss. Or do I miss your
point?
> The madvise manpage is also quite specific about not allowing
> MADV_DONTNEED and MADV_FREE for locked pages.
Yeah, but that seems to describe the state of the art rather than
explain why.
> So I don't think we should risk changing that for all mlocked pages.
> Maybe we can risk MCL_ONFAULT, since it's relatively new and has few users?
That is what Jason wanted but I argued that the two are the same from
MADV_DONTNEED point of view. I do not see how treating them differently
would be less confusing or error prone. It's new so we can make it
behave differently is certainly not an argument.
> >> So the more I think about it the more I am worried about this but I am
> >> more and more convinced that making ONFAULT special is just a wrong way
> >> around this.
> >>
> >
> > Ok, I share the concern that there is a chance that userspace is relying
> > on MADV_DONTNEED not free'ing locked memory. In that case, what if we
> > introduce a MADV_DONTNEED_FORCE, which does everything that
> > MADV_DONTNEED currently does but in addition will also free mlock areas.
> > That way there is no concern about breaking something.
>
> A new niche case flag? Sad :(
>
> BTW I didn't get why we should allow this for MADV_DONTNEED but not
> MADV_FREE. Can you expand on that?
Well, I wanted to bring this up as well. I guess this would require some
more hacks to handle the reclaim path correctly because we do rely on
VM_LOCK at many places for the lazy mlock pages culling.
--
Michal Hocko
SUSE Labs
^ permalink raw reply
* Re: [PATCH] mm/madvise: allow MADV_DONTNEED to free memory that is MLOCK_ONFAULT
From: Vlastimil Babka @ 2018-06-13 6:32 UTC (permalink / raw)
To: Jason Baron, Michal Hocko
Cc: akpm, linux-kernel, linux-mm, Joonsoo Kim, Mel Gorman,
Kirill A. Shutemov, linux-api, emunson
In-Reply-To: <5a9398f4-453c-5cb5-6bbc-f20c3affc96a@akamai.com>
On 06/12/2018 04:11 PM, Jason Baron wrote:
>
>
> On 06/12/2018 03:46 AM, Michal Hocko wrote:
>> On Mon 11-06-18 12:23:58, Jason Baron wrote:
>>> On 06/11/2018 11:03 AM, Michal Hocko wrote:
>>>> So can we start discussing whether we want to allow MADV_DONTNEED on
>>>> mlocked areas and what downsides it might have? Sure it would turn the
>>>> strong mlock guarantee to have the whole vma resident but is this
>>>> acceptable for something that is an explicit request from the owner of
>>>> the memory?
>>>>
>>>
>>> If its being explicity requested by the owner it makes sense to me. I
>>> guess there could be a concern about this breaking some userspace that
>>> relied on MADV_DONTNEED not freeing locked memory?
>>
>> Yes, this is always the fear when changing user visible behavior. I can
>> imagine that a userspace allocator calling MADV_DONTNEED on free could
>> break. The same would apply to MLOCK_ONFAULT/MCL_ONFAULT though. We
>> have the new flag much shorter so the probability is smaller but the
>> problem is very same. So I _think_ we should treat both the same because
>> semantically they are indistinguishable from the MADV_DONTNEED POV. Both
>> remove faulted and mlocked pages. Mlock, once applied, should guarantee
>> no later major fault and MADV_DONTNEED breaks that obviously.
I think more concerning than guaranteeing no later major fault is
possible data loss, e.g. replacing data with zero-filled pages.
The madvise manpage is also quite specific about not allowing
MADV_DONTNEED and MADV_FREE for locked pages.
So I don't think we should risk changing that for all mlocked pages.
Maybe we can risk MCL_ONFAULT, since it's relatively new and has few users?
>> So the more I think about it the more I am worried about this but I am
>> more and more convinced that making ONFAULT special is just a wrong way
>> around this.
>>
>
> Ok, I share the concern that there is a chance that userspace is relying
> on MADV_DONTNEED not free'ing locked memory. In that case, what if we
> introduce a MADV_DONTNEED_FORCE, which does everything that
> MADV_DONTNEED currently does but in addition will also free mlock areas.
> That way there is no concern about breaking something.
A new niche case flag? Sad :(
BTW I didn't get why we should allow this for MADV_DONTNEED but not
MADV_FREE. Can you expand on that?
> Thanks,
>
> -Jason
> --
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>
^ permalink raw reply
* Re: [PATCH v6 29/29] MAINTAINERS: add entry for FPGA DFL drivers
From: Alan Tull @ 2018-06-13 0:56 UTC (permalink / raw)
To: Wu Hao
Cc: Moritz Fischer, linux-fpga, linux-kernel, linux-api, Kang, Luwei,
Zhang, Yi Z
In-Reply-To: <1528798243-2029-30-git-send-email-hao.wu@intel.com>
On Tue, Jun 12, 2018 at 5:10 AM, Wu Hao <hao.wu@intel.com> wrote:
> Add entry for FPGA Device Feature List (DFL) drivers.
>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
> ---
> MAINTAINERS | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 448957c..98fc5ea 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5619,6 +5619,14 @@ F: drivers/fpga/
> F: include/linux/fpga/
> W: http://www.rocketboards.org
>
> +FPGA DFL DRIVERS
> +M: Wu Hao <hao.wu@intel.com>
> +L: linux-fpga@vger.kernel.org
> +S: Maintained
> +F: Documentation/fpga/dfl.txt
> +F: include/uapi/linux/fpga-dfl.h
> +F: drivers/fpga/dfl*
> +
> FPU EMULATOR
> M: Bill Metzenthen <billm@melbpc.org.au>
> W: http://floatingpoint.sourceforge.net/emulator/index.html
> --
> 1.8.3.1
>
^ permalink raw reply
* Re: [PATCH v6 12/29] fpga: add FPGA DFL PCIe device driver
From: Wu Hao @ 2018-06-12 23:42 UTC (permalink / raw)
To: Randy Dunlap
Cc: atull, mdf, linux-fpga, linux-kernel, linux-api, luwei.kang,
yi.z.zhang, Tim Whisonant, Enno Luebbers, Shiva Rao,
Christopher Rauer, Xiao Guangrong
In-Reply-To: <87a783f1-9db8-e56d-c4c4-1802c29c416a@infradead.org>
On Tue, Jun 12, 2018 at 08:27:27AM -0700, Randy Dunlap wrote:
> Hi,
>
> On 06/12/2018 03:10 AM, Wu Hao wrote:
> > From: Zhang Yi <yi.z.zhang@intel.com>
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index 4052532..5faab48 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -146,4 +146,19 @@ config FPGA_DFL
> > Gate Array (FPGA) solutions which implement Device Feature List.
> > It provides enumeration APIs, and feature device infrastructure.
> >
> > +config FPGA_DFL_PCI
> > + tristate "FPGA DFL PCIe Device Driver"
> > + depends on PCI && FPGA_DFL
> > + help
> > + Select this option to enable PCIe driver for PCIe based
>
> PCIe-based
>
> > + Field-Programmable Gate Array (FPGA) solutions which implemented
>
> which implement
Hi Randy
Thanks for the comments on these patches, I will fix them all in the next
version.
Hao
>
> > + the Device Feature List (DFL). This driver provides interfaces
> > + for userspace applications to configure, enumerate, open and access
> > + FPGA accelerators on the FPGA DFL devices, enables system level
> > + management functions such as FPGA partial reconfiguration, power
> > + management, and virtualization with DFL framework and DFL feature
> > + device drivers.
> > +
> > + To compile this as a module, choose M here.
> > +
> > endif # FPGA
>
>
> --
> ~Randy
^ permalink raw reply
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