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Tue, 14 Jan 2025 04:59:53 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 14 Jan 2025 10:59:33 +0100 From: "Arnd Bergmann" To: "Geert Uytterhoeven" , "Jiaxun Yang" Cc: =?UTF-8?Q?Mateusz_Jo=C5=84czyk?= , "linux-mips@vger.kernel.org" , Linux-Arch , linux-kernel@vger.kernel.org, "Baoquan He" , "Thomas Bogendoerfer" , "Alexandre Belloni" , regressions@lists.linux.dev Message-Id: <08fe1ebb-b9c4-46c7-a6ab-5a336ec3b771@app.fastmail.com> In-Reply-To: References: <90b5b76d-25b6-4cdc-91ed-07ac930dc519@o2.pl> <99f75c66-4c2d-45dc-a808-b5ba440c7551@app.fastmail.com> Subject: Re: [REGRESSION] mipsel: no RTC CMOS on the Malta platform in QEMU Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Tue, Jan 14, 2025, at 09:02, Geert Uytterhoeven wrote: > On Tue, Jan 14, 2025 at 12:32=E2=80=AFAM Jiaxun Yang wrote: >> =E5=9C=A82025=E5=B9=B41=E6=9C=8813=E6=97=A5=E4=B8=80=E6=9C=88 =E4=B8=8B= =E5=8D=8810:16=EF=BC=8CMateusz Jo=C5=84czyk=E5=86=99=E9=81=93=EF=BC=9A >> > #ifndef PCI_IOBASE >> > #define PCI_IOBASE ((void __iomem *)0) >> > #endif >> > >> > That PCI_IOBASE value above is AFAIK incorrect for MIPS (it should = be >> > defined to mips_io_port_base as far as I can tell), but this does n= ot >> > matter much here. >> >> You are right, this is what should be done. >> >> A quick fix would be #undef PCI_IOBASE in arch/mips/include/asm/io.h >> just after including #include , with ralink and loo= ngson64 >> as exception. > > Shouldn't arch/mips/include/asm/io.h do > > #define PCI_IOBASE mips_io_port_base > > unconditionally, _before_ including ? Yes, I think this would make the most sense, but the ordering with the PCI initialization needs to be done carefully, to ensure that PCI_IOBASE has its final value before the first call to pci_remap_iospace(). >> In the long term, we should scrutinize platform usage of mips_io_base >> following ralink's approach. > > Currently ralink handles that in a mach-specific include: > > arch/mips/include/asm/mach-ralink/spaces.h:#define PCI_IOBASE > mips_io_port_base > > Loongson does it differently: > > arch/mips/include/asm/mach-loongson64/spaces.h:#define PCI_IOBASE > _AC(0xc000000000000000 + SZ_128K, UL) > > But still sets mips_io_port_base in prom_init(): > > arch/mips/loongson64/init.c: set_io_port_base(PCI_IOBASE); > > so defining PCI_IOBASE to mips_io_port_base in the main > should work. This probably requires calling set_io_port_base() with the actual virtual address rather than self-assigning the uninitialized mips_io_port_base. I assume the reason for loongson64 being different from every other mips platform is the same as why it calls into the logic_pio_register_range() directly. I don't understand that code, but it's probably because it has ISA/LPC devices that are directly wired to a non-memory-mapped set of registers instead of them being behind a PCI bridge like the other platforms. The idea of logic_pio is to have a more generic way to redirect arbitrary port ranges into bus specific function calls, where normal PCI (on non-x86) assumes that all I/O ports are mapped into a small contiguous ranges of virtual addresses. Arnd