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Subject: Re: Alpha Avanti broken by 9ce8654323d69273b4977f76f11c9e2d345ab130
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From: Sinan Kaya <okaya@codeaurora.org>
Message-ID: <09c561cf-541c-219a-f19b-4ecfaf9a0f02@codeaurora.org>
Date: Wed, 22 Aug 2018 15:38:46 -0400
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To: Mikulas Patocka <mpatocka@redhat.com>, Arnd Bergmann <arnd@arndb.de>
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>, Matt Turner <mattst88@gmail.com>, linux-alpha@vger.kernel.org, okaya@kernel.org, Will Deacon <will.deacon@arm.com>, linux-arch <linux-arch@vger.kernel.org>, Peter Zijlstra <peterz@infradead.org>, Thomas Gleixner <tglx@linutronix.de>

On 8/22/2018 1:47 PM, Mikulas Patocka wrote:
> If ARM guarantees that the accesses to a given device are not reordered -
> then the barriers in readl and writel are superfluous.

It is not. ARM only guarantees ordering of read/write transactions targeting
a device not memory.

example:

write memory
raw write to device

or

raw read from device
read memory

these can bypass each other on ARM unless a barrier is placed in the right
place either via readl()/writel() or explicitly.


raw write to device
raw write to device

or

raw write to device
raw read from device

or

raw read from device
raw read from device

are guaranteed to be ordered on ARM without needing any explicit barrier.