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Tue, 5 Jan 2021 03:09:47 -0800 Envelope-to: michal.simek@xilinx.com, srinivas.neeli@xilinx.com, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arch@vger.kernel.org, amit.kucheria@verdurent.com, daniel.lezcano@linaro.org, rui.zhang@intel.com, akpm@linux-foundation.org, yamada.masahiro@socionext.com, bgolaszewski@baylibre.com, rrichter@marvell.com, arnd@arndb.de, vilhelm.gray@gmail.com, andriy.shevchenko@linux.intel.com, linus.walleij@linaro.org, syednwaris@gmail.com Received: from [172.30.17.109] (port=46342) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kwkDi-0000GS-ME; Tue, 05 Jan 2021 03:09:47 -0800 To: Syed Nayyar Waris , , Srinivas Neeli CC: , , , , , , , , , , , , , , , References: From: Michal Simek Subject: Re: [PATCH 0/5] Introduce the for_each_set_clump macro Message-ID: <0ddb32ad-c330-b1d5-34e0-5b24611a4d1f@xilinx.com> Date: Tue, 5 Jan 2021 12:09:41 +0100 User-Agent: Mozilla/5.0 (X11; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2021 11:09:48.2780 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3407ca10-4cc5-4257-4681-08d8b16a6a74 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT044.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB4352 Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org Hi, On 26. 12. 20 7:41, Syed Nayyar Waris wrote: > Hello Linus, > > Since this patchset primarily affects GPIO drivers, would you like > to pick it up through your GPIO tree? > > (Note: Patchset resent with the new macro and relevant > functions shifted to a new header clump_bits.h [Linus Torvalds]) > > Michal, > What do you think of [PATCH 5/5]? Is the conditional check needed? And > also does returning -EINVAL look good? As was said would be better to handle it out of this series. And I expect none is really describing fpga designs by hand and using DT generator for it. But I can't see any issue with checking that we are not exceeding certain limit. Just keep in your mind that every bank has max 32 lines. It means if you say bank0 40, bank1 10 which is in total 50 it will pass your condition in 5/5. It means maybe checking every bank separately is better approach. Thanks, Michal