From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from stat16.steeleye.com ([209.192.50.48]:18092 "EHLO hancock.sc.steeleye.com") by vger.kernel.org with ESMTP id S268237AbUIPUiB (ORCPT ); Thu, 16 Sep 2004 16:38:01 -0400 Subject: Re: RFC: being more anal about iospace accesses.. From: James Bottomley In-Reply-To: <200409161302.49135.jbarnes@engr.sgi.com> References: <200409161152.54691.jbarnes@engr.sgi.com> <200409161302.49135.jbarnes@engr.sgi.com> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: 16 Sep 2004 16:37:23 -0400 Message-Id: <1095367049.2014.21.camel@mulgrave> Mime-Version: 1.0 To: Jesse Barnes Cc: Linus Torvalds , Matthew Wilcox , Geert Uytterhoeven , Linux Arch list , Al Viro , Andrew Morton , Alan Cox , "David S. Miller" , Jeff Garzik , Grant Grundler List-ID: On Thu, 2004-09-16 at 16:02, Jesse Barnes wrote: > Note that PCI-X and PCI Express allow a lack of synchronization via the > relaxed ordering bit. So platforms can either set that bit in their iomap > functions and deal with synchronization via dma_sync or not use it I guess. Now you've confused me again. I thought the SGI implementation of this relaxed read thing was *not* the same as the PCI-X RO bit which was why you needed a special readX_relaxed? My understanding is that Relaxed Ordering is that it's two bit (i.e. two separately allowable optimisations) that allow either PIO writes to pass DMA reads or PIO reads to pass DMA writes (or both) in the stream (I may have this wrong, I copied Grant because he's been working on this). I thought your readX_relaxed was only the first half of this? James