From: James Bottomley <James.Bottomley@steeleye.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Andi Kleen <ak@suse.de>,
Martin Schwidefsky <schwidefsky@de.ibm.com>,
linux-arch@vger.kernel.org
Subject: Re: 4level page tables architecture porting
Date: 20 Oct 2004 11:25:35 -0500 [thread overview]
Message-ID: <1098289545.2009.17.camel@mulgrave> (raw)
In-Reply-To: <200410201706.00435.arnd@arndb.de>
On Wed, 2004-10-20 at 10:05, Arnd Bergmann wrote:
> Doesn't that mean spending another page for each running process? I would
> rather like to see a way to use a dynamic page table layout, where 32 bit
> tasks always use only two level page tables, while 64 bit tasks start
> with two or three levels and then go to four or five levels when users
> map files that don't fit in.
Actually, the kicker (at least for software TLB architectures) is
another lookup in the TLB insertion handler. We actually run a hybrid
scheme on parisc for this reason---compat 32 processes only get a
2-Level page table even on 64 bit kernels. That was also the reason for
all the theoretical work on different types of page tables.
James
next prev parent reply other threads:[~2004-10-20 16:25 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-10-20 13:13 4level page tables architecture porting Martin Schwidefsky
2004-10-20 14:39 ` Andi Kleen
2004-10-20 15:05 ` Arnd Bergmann
2004-10-20 15:17 ` Geert Uytterhoeven
2004-10-20 15:29 ` Andi Kleen
2004-10-20 16:17 ` Martin Schwidefsky
2004-10-20 16:25 ` James Bottomley [this message]
2004-10-20 16:42 ` Martin Schwidefsky
2004-10-20 21:32 ` James Bottomley
-- strict thread matches above, loose matches on Subject: below --
2004-10-20 16:23 Luck, Tony
2004-10-15 15:21 Andi Kleen
2004-10-15 18:06 ` David Woodhouse
2004-10-15 19:32 ` Andi Kleen
2004-10-15 19:37 ` David Woodhouse
2004-10-15 21:41 ` David Woodhouse
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