From: James Bottomley <James.Bottomley@steeleye.com>
To: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Andi Kleen <ak@suse.de>, Arnd Bergmann <arnd@arndb.de>,
linux-arch@vger.kernel.org
Subject: Re: 4level page tables architecture porting
Date: 20 Oct 2004 16:32:15 -0500 [thread overview]
Message-ID: <1098307940.1765.16.camel@mulgrave> (raw)
In-Reply-To: <OF14AD849F.49584F04-ON42256F33.005B3FB1-42256F33.005BC93B@de.ibm.com>
On Wed, 2004-10-20 at 11:42, Martin Schwidefsky wrote:
> So you do run a hybrid scheme on parisc, that is interesting. I'm probably
> going to copy some of the parisc code to s390 then. We do want to have this
> for our 31-bit processes on a 64 bit kernel.
Feel free, but the price of our scheme is moderately high. In order to
fit eight byte pointers in a two level scheme, we only use 32 bit
pointers in the pgd (originally we enforced this by making all our pte
pages come out of GFP_DMA which is under 4GB on parisc, but now we use a
bit shift scheme that theoretically will last us up to the bus physical
limit of the latest pa8800 chipset [several terrabytes at least]); Even
so, our pgd has to be an order 1 allocation (although being one per
process, it's not such a burden).
James
next prev parent reply other threads:[~2004-10-20 21:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-10-20 13:13 4level page tables architecture porting Martin Schwidefsky
2004-10-20 14:39 ` Andi Kleen
2004-10-20 15:05 ` Arnd Bergmann
2004-10-20 15:17 ` Geert Uytterhoeven
2004-10-20 15:29 ` Andi Kleen
2004-10-20 16:17 ` Martin Schwidefsky
2004-10-20 16:25 ` James Bottomley
2004-10-20 16:42 ` Martin Schwidefsky
2004-10-20 21:32 ` James Bottomley [this message]
-- strict thread matches above, loose matches on Subject: below --
2004-10-20 16:23 Luck, Tony
2004-10-15 15:21 Andi Kleen
2004-10-15 18:06 ` David Woodhouse
2004-10-15 19:32 ` Andi Kleen
2004-10-15 19:37 ` David Woodhouse
2004-10-15 21:41 ` David Woodhouse
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