From mboxrd@z Thu Jan 1 00:00:00 1970 From: Geert Uytterhoeven Subject: Re: [CFT] MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself Date: Wed, 20 Jan 2010 17:45:34 +0100 Message-ID: <10f740e81001200845o7a31bcb6yea475f3aabcb5476@mail.gmail.com> References: <20100120135202.GA20937@flint.arm.linux.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <20100120135202.GA20937@flint.arm.linux.org.uk> Sender: linux-kernel-owner@vger.kernel.org To: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-arch.vger.kernel.org On Wed, Jan 20, 2010 at 14:52, Russell King = wrote: > On VIVT ARM, when we have multiple shared mappings of the same file > in the same MM, we need to ensure that we have coherency across all > copies. =C2=A0We do this via make_coherent() by making the pages > uncacheable. > > This used to work fine, until we allowed highmem with highpte - we > now have a page table which is mapped as required, and is not availab= le > for modification via update_mmu_cache(). > > Ralf Beache suggested getting rid of the PTE value passed to > update_mmu_cache(): > > =C2=A0On MIPS update_mmu_cache() calls __update_tlb() which walks pag= etables > =C2=A0to construct a pointer to the pte again. =C2=A0Passing a pte_t = * is much > =C2=A0more elegant. =C2=A0Maybe we might even replace the pte argumen= t with the > =C2=A0pte_t? > > Ben Herrenschmidt would also like the pte pointer for PowerPC: > > =C2=A0Passing the ptep in there is exactly what I want. =C2=A0I want = that > =C2=A0-instead- of the PTE value, because I have issue on some ppc ca= ses, > =C2=A0for I$/D$ coherency, where set_pte_at() may decide to mask out = the > =C2=A0_PAGE_EXEC. > > So, pass in the mapped page table pointer into update_mmu_cache(), an= d > remove the PTE value, updating all implementations and call sites to > suit. > diff --git a/Documentation/cachetlb.txt b/Documentation/cachetlb.txt > index da42ab4..74a8b6f 100644 > --- a/Documentation/cachetlb.txt > +++ b/Documentation/cachetlb.txt > @@ -88,12 +88,12 @@ changes occur: > =C2=A0 =C2=A0 =C2=A0 =C2=A0This is used primarily during fault proces= sing. > > =C2=A05) void update_mmu_cache(struct vm_area_struct *vma, > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0unsigned long address, pte_t pte) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0unsigned long address, pte_t *ptep) > > =C2=A0 =C2=A0 =C2=A0 =C2=A0At the end of every page fault, this routi= ne is invoked to > =C2=A0 =C2=A0 =C2=A0 =C2=A0tell the architecture specific code that a= translation > - =C2=A0 =C2=A0 =C2=A0 described by "pte" now exists at virtual addre= ss "address" > - =C2=A0 =C2=A0 =C2=A0 for address space "vma->vm_mm", in the softwar= e page tables. > + =C2=A0 =C2=A0 =C2=A0 now exists at virtual address "address" for ad= dress space > + =C2=A0 =C2=A0 =C2=A0 "vma->vm_mm", in the software page tables. > > =C2=A0 =C2=A0 =C2=A0 =C2=A0A port may use this information in any way= it so chooses. > =C2=A0 =C2=A0 =C2=A0 =C2=A0For example, it could use this event to pr= e-load TLB Now the documentation no longer mentions what the 3rd parameter is used= for? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-= m68k.org In personal conversations with technical people, I call myself a hacker= =2E But when I'm talking to journalists I just say "programmer" or something li= ke that. -- Linus Torvalds From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ew0-f209.google.com ([209.85.219.209]:56912 "EHLO mail-ew0-f209.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750703Ab0ATQpg convert rfc822-to-8bit (ORCPT ); Wed, 20 Jan 2010 11:45:36 -0500 MIME-Version: 1.0 In-Reply-To: <20100120135202.GA20937@flint.arm.linux.org.uk> References: <20100120135202.GA20937@flint.arm.linux.org.uk> Date: Wed, 20 Jan 2010 17:45:34 +0100 Message-ID: <10f740e81001200845o7a31bcb6yea475f3aabcb5476@mail.gmail.com> Subject: Re: [CFT] MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself From: Geert Uytterhoeven Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-arch-owner@vger.kernel.org List-ID: To: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Message-ID: <20100120164534.gtix_vawhzCf6dM2R8GLdBwLxKNaekcQf2ABYa-OgbA@z> On Wed, Jan 20, 2010 at 14:52, Russell King wrote: > On VIVT ARM, when we have multiple shared mappings of the same file > in the same MM, we need to ensure that we have coherency across all > copies.  We do this via make_coherent() by making the pages > uncacheable. > > This used to work fine, until we allowed highmem with highpte - we > now have a page table which is mapped as required, and is not available > for modification via update_mmu_cache(). > > Ralf Beache suggested getting rid of the PTE value passed to > update_mmu_cache(): > >  On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables >  to construct a pointer to the pte again.  Passing a pte_t * is much >  more elegant.  Maybe we might even replace the pte argument with the >  pte_t? > > Ben Herrenschmidt would also like the pte pointer for PowerPC: > >  Passing the ptep in there is exactly what I want.  I want that >  -instead- of the PTE value, because I have issue on some ppc cases, >  for I$/D$ coherency, where set_pte_at() may decide to mask out the >  _PAGE_EXEC. > > So, pass in the mapped page table pointer into update_mmu_cache(), and > remove the PTE value, updating all implementations and call sites to > suit. > diff --git a/Documentation/cachetlb.txt b/Documentation/cachetlb.txt > index da42ab4..74a8b6f 100644 > --- a/Documentation/cachetlb.txt > +++ b/Documentation/cachetlb.txt > @@ -88,12 +88,12 @@ changes occur: >        This is used primarily during fault processing. > >  5) void update_mmu_cache(struct vm_area_struct *vma, > -                        unsigned long address, pte_t pte) > +                        unsigned long address, pte_t *ptep) > >        At the end of every page fault, this routine is invoked to >        tell the architecture specific code that a translation > -       described by "pte" now exists at virtual address "address" > -       for address space "vma->vm_mm", in the software page tables. > +       now exists at virtual address "address" for address space > +       "vma->vm_mm", in the software page tables. > >        A port may use this information in any way it so chooses. >        For example, it could use this event to pre-load TLB Now the documentation no longer mentions what the 3rd parameter is used for? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds