From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Subject: Re: [PATCH 1/12]: MUTEX: Implement mutexes From: Alan Cox In-Reply-To: References: <200512162313.jBGND7g4019623@warthog.cambridge.redhat.com> <1134791914.13138.167.camel@localhost.localdomain> <14917.1134847311@warthog.cambridge.redhat.com> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Sun, 18 Dec 2005 13:38:13 +0000 Message-Id: <1134913093.26141.30.camel@localhost.localdomain> Mime-Version: 1.0 To: Nicolas Pitre Cc: Linus Torvalds , David Howells , Steven Rostedt , linux-arch@vger.kernel.org, lkml , mingo@redhat.com, Andrew Morton List-ID: On Sad, 2005-12-17 at 20:29 -0500, Nicolas Pitre wrote: > out there. The other 99% of actual ARM processors in the field only > have the atomic swap (swp) instruction which is insufficient for > implementing a counting semaphore (we therefore have to disable > interrupts, do the semaphore update and enable interrupts again which is > much slower than a swp-based mutex). There are other approaches depending on how your CPU behaves and the probability of splitting an "atomic operation" including checking the return address range in the IRQ handler and ifs its in the 'atomic ops' page jumping to a recovery function. If you are sneaky in how you lay out your virtual address space it becomes a single unconditional or on kernel->kernel interrupt returns.