Re: Q: smp.c && barriers (Was: [PATCH 1/4] generic-smp: remove single ipi fallback for smp_call_function_many())

Linus Torvalds
2009-02-18T16:10:47Z

On Wed, 18 Feb 2009, Nick Piggin wrote:
>
> I agree with you both that we *should* make arch interrupt code
> do the ordering, but given the subtle lockups on some architectures
> in this new code, I didn't want to make it significantly weaker...
>
> Though perhaps it appears that I have, if I have removed an smp_mb
> that x86 was relying on to emit an mfence to serialise the apic.

The thing is, if the architecture doesn't order IPI wrt cache coherency,
then the "smp_mb()" doesn't really do so _either_.

It might hide some architecture-specific implementation issue, of course,
so random amounts of "smp_mb()"s sprinkled around might well make some
architecture "work", but it's in no way guaranteed. A smp_mb() does not
guarantee that some separate IPI network is ordered - that may well take
some random machine-specific IO cycle.

That said, at least on x86, taking an interrupt should be a serializing
event, so there should be no reason for anything on the receiving side.
The _sending_ side might need to make sure that there is serialization
when generating the IPI (so that the IPI cannot happen while the writes
are still in some per-CPU write buffer and haven't become part of the
cache coherency domain).

And at least on x86 it's actually pretty hard to generate out-of-order
accesses to begin with (_regardless_ of any issues external to the CPU).
You have to work at it, and use a WC memory area, and I'm pretty sure we
use UC for the apic accesses.

Linus