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From: Peter Zijlstra <a.p.zijlstra@chello.nl>
Subject: Re: [PATCH v5 6/7] x86/tlb: optimizing flush_tlb_mm
Date: Tue, 15 May 2012 15:06:10 +0200
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To: Luming Yu <luming.yu@gmail.com>
Cc: Nick Piggin <npiggin@gmail.com>, Alex Shi <alex.shi@intel.com>, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, arnd@arndb.de, rostedt@goodmis.org, fweisbec@gmail.com, jeremy@goop.org, riel@redhat.com, luto@mit.edu, avi@redhat.com, len.brown@intel.com, dhowells@redhat.com, fenghua.yu@intel.com, borislav.petkov@amd.com, yinghai@kernel.org, ak@linux.intel.com, cpw@sgi.com, steiner@sgi.com, akpm@linux-foundation.org, penberg@kernel.org, hughd@google.com, rientjes@google.com, kosaki.motohiro@jp.fujitsu.com, n-horiguchi@ah.jp.nec.com, tj@kernel.org, oleg@redhat.com, axboe@kernel.dk, jmorris@namei.org, kamezawa.hiroyu@jp.fujitsu.com, viro@zeniv.linux.org.uk, linux-kernel@vger.kernel.org, yongjie.ren@intel.com, linux-arch@vger.kernel.org, jcm@jonmasters.org

On Tue, 2012-05-15 at 20:58 +0800, Luming Yu wrote:
> 
> 
> Both __native_flush_tlb() and __native_flush_tlb_single(...)
> introduced roughly 1 ns  latency to tsc sampling executed in
> stop_machine_context in two logical CPUs 

But you have to weight that against the cost of re-population, and
that's the difficult bit, since we have no clue how many tlb entries are
in use by the current cr3.

It might be possible for intel to give us this information, I've asked
for something similar for cachelines.