From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yijing Wang Subject: [PATCH v3 17/27] MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq Date: Wed, 15 Oct 2014 11:07:05 +0800 Message-ID: <1413342435-7876-18-git-send-email-wangyijing@huawei.com> References: <1413342435-7876-1-git-send-email-wangyijing@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1413342435-7876-1-git-send-email-wangyijing-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Bjorn Helgaas Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org, linux-ia64-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Thierry Reding , sparclinux-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arch-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-s390-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King , Michael Ellerman , x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Sebastian Ott , Benjamin Herrenschmidt , xen-devel-GuqFBffKawtpuQazS67q72D2FQJk+8+b@public.gmane.org, arnab.basu-KZfg59tc24xl57MIdRCFDg@public.gmane.org, Liviu Dudau , Arnd Bergmann , Chris Metcalf , Thomas Gleixner , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Thomas Petazzoni , Xinwei Hu , Tony Luck , Sergei Shtylyov , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Ralf Baechle , iommu@l List-Id: linux-arch.vger.kernel.org Use MSI chip framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/mips/include/asm/octeon/pci-octeon.h | 4 +++ arch/mips/pci/msi-octeon.c | 31 ++++++++++++++++------------ arch/mips/pci/pci-octeon.c | 3 ++ 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h index 64ba56a..27ffe42 100644 --- a/arch/mips/include/asm/octeon/pci-octeon.h +++ b/arch/mips/include/asm/octeon/pci-octeon.h @@ -66,4 +66,8 @@ enum octeon_dma_bar_type { */ extern enum octeon_dma_bar_type octeon_dma_bar_type; +#ifdef CONFIG_PCI_MSI +extern struct msi_chip octeon_msi_chip; +#endif + #endif diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index 63bbe07..fd4d698 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -57,7 +57,7 @@ static int msi_irq_size; * * Returns 0 on success. */ -int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) +static int octeon_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) { struct msi_msg msg; u16 control; @@ -132,12 +132,12 @@ msi_irq_allocated: /* Make sure the search for available interrupts didn't fail */ if (irq >= 64) { if (request_private_bits) { - pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one", - 1 << request_private_bits); + pr_err("%s: Unable to find %d free interrupts, trying just one", + __func__, 1 << request_private_bits); request_private_bits = 0; goto try_only_one; } else - panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); + panic("%s: Unable to find a free MSI interrupt", __func__); } /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */ @@ -168,7 +168,7 @@ msi_irq_allocated: msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32; break; default: - panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type"); + panic("%s: Invalid octeon_dma_bar_type", __func__); } msg.data = irq - OCTEON_IRQ_MSI_BIT0; @@ -182,7 +182,8 @@ msi_irq_allocated: return 0; } -int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +static int octeon_setup_msi_irqs(struct msi_chip *chip, struct pci_dev *dev, + int nvec, int type) { struct msi_desc *entry; int ret; @@ -201,7 +202,7 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) return 1; list_for_each_entry(entry, &dev->msi_list, list) { - ret = arch_setup_msi_irq(dev, entry); + ret = octeon_setup_msi_irq(dev, entry); if (ret < 0) return ret; if (ret > 0) @@ -210,14 +211,13 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) return 0; } - /** * Called when a device no longer needs its MSI interrupts. All * MSI interrupts for the device are freed. * * @irq: The devices first irq number. There may be multple in sequence. */ -void arch_teardown_msi_irq(unsigned int irq) +static void octeon_teardown_msi_irq(struct msi_chip *chip, unsigned int irq) { int number_irqs; u64 bitmask; @@ -226,8 +226,8 @@ void arch_teardown_msi_irq(unsigned int irq) if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0)) - panic("arch_teardown_msi_irq: Attempted to teardown illegal " - "MSI interrupt (%d)", irq); + panic("%s: Attempted to teardown illegal " + "MSI interrupt (%d)", __func__, irq); irq -= OCTEON_IRQ_MSI_BIT0; index = irq / 64; @@ -249,8 +249,8 @@ void arch_teardown_msi_irq(unsigned int irq) /* Shift the mask to the correct bit location */ bitmask <<= irq0; if ((msi_free_irq_bitmask[index] & bitmask) != bitmask) - panic("arch_teardown_msi_irq: Attempted to teardown MSI " - "interrupt (%d) not in use", irq); + panic("%s: Attempted to teardown MSI " + "interrupt (%d) not in use", __func__, irq); /* Checks are done, update the in use bitmask */ spin_lock(&msi_free_irq_bitmask_lock); @@ -259,6 +259,11 @@ void arch_teardown_msi_irq(unsigned int irq) spin_unlock(&msi_free_irq_bitmask_lock); } +struct msi_chip octeon_msi_chip = { + .setup_irqs = octeon_setup_msi_irqs, + .teardown_irq = octeon_teardown_msi_irq, +}; + static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); static u64 msi_rcv_reg[4]; diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 59cccd9..aefaa8a 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -356,6 +356,9 @@ static struct pci_controller octeon_pci_controller = { .io_resource = &octeon_pci_io_resource, .io_offset = 0, .io_map_base = OCTEON_PCI_IOSPACE_BASE, +#ifdef CONFIG_PCI_MSI + .msi_chip = &octeon_msi_chip, +#endif }; -- 1.7.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from szxga03-in.huawei.com ([119.145.14.66]:56240 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932773AbaJOC0F (ORCPT ); Tue, 14 Oct 2014 22:26:05 -0400 From: Yijing Wang Subject: [PATCH v3 17/27] MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq Date: Wed, 15 Oct 2014 11:07:05 +0800 Message-ID: <1413342435-7876-18-git-send-email-wangyijing@huawei.com> In-Reply-To: <1413342435-7876-1-git-send-email-wangyijing@huawei.com> References: <1413342435-7876-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-arch-owner@vger.kernel.org List-ID: To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Xinwei Hu , Wuyun , linux-arm-kernel@lists.infradead.org, Russell King , linux-arch@vger.kernel.org, arnab.basu@freescale.com, Bharat.Bhushan@freescale.com, x86@kernel.org, Arnd Bergmann , Thomas Gleixner , Konrad Rzeszutek Wilk , xen-devel@lists.xenproject.org, Joerg Roedel , iommu@lists.linux-foundation.org, linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, Sebastian Ott , Tony Luck , linux-ia64@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , Sergei Shtylyov , Michael Ellerman , Thierry Reding , Thomas Petazzoni , Liviu Dudau , Yijing Wang Message-ID: <20141015030705.bZX6w0pbt7RRkBBl1RXxrAanq99ZgjQm2fuKfQBq284@z> Use MSI chip framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/mips/include/asm/octeon/pci-octeon.h | 4 +++ arch/mips/pci/msi-octeon.c | 31 ++++++++++++++++------------ arch/mips/pci/pci-octeon.c | 3 ++ 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h index 64ba56a..27ffe42 100644 --- a/arch/mips/include/asm/octeon/pci-octeon.h +++ b/arch/mips/include/asm/octeon/pci-octeon.h @@ -66,4 +66,8 @@ enum octeon_dma_bar_type { */ extern enum octeon_dma_bar_type octeon_dma_bar_type; +#ifdef CONFIG_PCI_MSI +extern struct msi_chip octeon_msi_chip; +#endif + #endif diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index 63bbe07..fd4d698 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -57,7 +57,7 @@ static int msi_irq_size; * * Returns 0 on success. */ -int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) +static int octeon_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) { struct msi_msg msg; u16 control; @@ -132,12 +132,12 @@ msi_irq_allocated: /* Make sure the search for available interrupts didn't fail */ if (irq >= 64) { if (request_private_bits) { - pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one", - 1 << request_private_bits); + pr_err("%s: Unable to find %d free interrupts, trying just one", + __func__, 1 << request_private_bits); request_private_bits = 0; goto try_only_one; } else - panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); + panic("%s: Unable to find a free MSI interrupt", __func__); } /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */ @@ -168,7 +168,7 @@ msi_irq_allocated: msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32; break; default: - panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type"); + panic("%s: Invalid octeon_dma_bar_type", __func__); } msg.data = irq - OCTEON_IRQ_MSI_BIT0; @@ -182,7 +182,8 @@ msi_irq_allocated: return 0; } -int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +static int octeon_setup_msi_irqs(struct msi_chip *chip, struct pci_dev *dev, + int nvec, int type) { struct msi_desc *entry; int ret; @@ -201,7 +202,7 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) return 1; list_for_each_entry(entry, &dev->msi_list, list) { - ret = arch_setup_msi_irq(dev, entry); + ret = octeon_setup_msi_irq(dev, entry); if (ret < 0) return ret; if (ret > 0) @@ -210,14 +211,13 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) return 0; } - /** * Called when a device no longer needs its MSI interrupts. All * MSI interrupts for the device are freed. * * @irq: The devices first irq number. There may be multple in sequence. */ -void arch_teardown_msi_irq(unsigned int irq) +static void octeon_teardown_msi_irq(struct msi_chip *chip, unsigned int irq) { int number_irqs; u64 bitmask; @@ -226,8 +226,8 @@ void arch_teardown_msi_irq(unsigned int irq) if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0)) - panic("arch_teardown_msi_irq: Attempted to teardown illegal " - "MSI interrupt (%d)", irq); + panic("%s: Attempted to teardown illegal " + "MSI interrupt (%d)", __func__, irq); irq -= OCTEON_IRQ_MSI_BIT0; index = irq / 64; @@ -249,8 +249,8 @@ void arch_teardown_msi_irq(unsigned int irq) /* Shift the mask to the correct bit location */ bitmask <<= irq0; if ((msi_free_irq_bitmask[index] & bitmask) != bitmask) - panic("arch_teardown_msi_irq: Attempted to teardown MSI " - "interrupt (%d) not in use", irq); + panic("%s: Attempted to teardown MSI " + "interrupt (%d) not in use", __func__, irq); /* Checks are done, update the in use bitmask */ spin_lock(&msi_free_irq_bitmask_lock); @@ -259,6 +259,11 @@ void arch_teardown_msi_irq(unsigned int irq) spin_unlock(&msi_free_irq_bitmask_lock); } +struct msi_chip octeon_msi_chip = { + .setup_irqs = octeon_setup_msi_irqs, + .teardown_irq = octeon_teardown_msi_irq, +}; + static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); static u64 msi_rcv_reg[4]; diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 59cccd9..aefaa8a 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -356,6 +356,9 @@ static struct pci_controller octeon_pci_controller = { .io_resource = &octeon_pci_io_resource, .io_offset = 0, .io_map_base = OCTEON_PCI_IOSPACE_BASE, +#ifdef CONFIG_PCI_MSI + .msi_chip = &octeon_msi_chip, +#endif }; -- 1.7.1