From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Martin Subject: [PATCH v3 24/28] arm64/sve: KVM: Hide SVE from CPU features exposed to guests Date: Tue, 10 Oct 2017 19:38:41 +0100 Message-ID: <1507660725-7986-25-git-send-email-Dave.Martin@arm.com> References: <1507660725-7986-1-git-send-email-Dave.Martin@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1507660725-7986-1-git-send-email-Dave.Martin@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: linux-arm-kernel@lists.infradead.org Cc: linux-arch@vger.kernel.org, Okamoto Takayuki , libc-alpha@sourceware.org, Ard Biesheuvel , Szabolcs Nagy , Catalin Marinas , Will Deacon , Marc Zyngier , Richard Sandiford , kvmarm@lists.cs.columbia.edu List-Id: linux-arch.vger.kernel.org S1ZNIGd1ZXN0cyBjYW5ub3QgY3VycmVudGx5IHVzZSBTVkUsIGJlY2F1c2UgU1ZFIGlzIGFsd2F5 cwpjb25maWd1cmVkIHRvIHRyYXAgdG8gRUwyLgoKSG93ZXZlciwgYSBndWVzdCB0aGF0IHNlZXMg U1ZFIHJlcG9ydGVkIGFzIHByZXNlbnQgaW4KSURfQUE2NFBGUjBfRUwxIG1heSBsZWdpdGltYXRl bHkgZXhwZWN0IHRoYXQgU1ZFIHdvcmtzIGFuZCB0cnkgdG8KdXNlIGl0LiAgSW5zdGVhZCBvZiB3 b3JraW5nLCB0aGUgZ3Vlc3Qgd2lsbCByZWNlaXZlIGFuIGluamVjdGVkCnVuZGVmIGV4Y2VwdGlv biwgd2hpY2ggbWF5IGNhdXNlIHRoZSBndWVzdCB0byBvb3BzIG9yIGdvIGludG8gYQpzcGluLgoK VG8gYXZvaWQgbWlzbGVhZGluZyB0aGUgZ3Vlc3QgaW50byBiZWxpZXZpbmcgdGhhdCBTVkUgd2ls bCB3b3JrLAp0aGlzIHBhdGNoIG1hc2tzIG91dCB0aGUgU1ZFIGZpZWxkIGZyb20gSURfQUE2NFBG UjBfRUwxIHdoZW4gYQpndWVzdCBhdHRlbXB0cyB0byByZWFkIHRoaXMgcmVnaXN0ZXIuICBObyBz dXBwb3J0IGlzIGV4cGxpY2l0bHkKYWRkZWQgZm9yIElEX0FBNjRaRlIwX0VMMSBlaXRoZXIsIHNv IHRoYXQgaXMgc3RpbGwgZW11bGF0ZWQgYXMKcmVhZGluZyBhcyB6ZXJvLCB3aGljaCBpcyBjb25z aXN0ZW50IHdpdGggU1ZFIG5vdCBiZWluZwppbXBsZW1lbnRlZC4KClRoaXMgaXMgYSB0ZW1wb3Jh cnkgbWVhc3VyZSwgYW5kIHdpbGwgYmUgcmVtb3ZlZCBpbiBhIGxhdGVyIHNlcmllcwp3aGVuIGZ1 bGwgS1ZNIHN1cHBvcnQgZm9yIFNWRSBpcyBpbXBsZW1lbnRlZC4KClNpZ25lZC1vZmYtYnk6IERh dmUgTWFydGluIDxEYXZlLk1hcnRpbkBhcm0uY29tPgpSZXZpZXdlZC1ieTogQWxleCBCZW5uw6ll IDxhbGV4LmJlbm5lZUBsaW5hcm8ub3JnPgpDYzogTWFyYyBaeW5naWVyIDxtYXJjLnp5bmdpZXJA YXJtLmNvbT4KLS0tCiBhcmNoL2FybTY0L2t2bS9zeXNfcmVncy5jIHwgMTIgKysrKysrKysrKyst CiAxIGZpbGUgY2hhbmdlZCwgMTEgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQoKZGlmZiAt LWdpdCBhL2FyY2gvYXJtNjQva3ZtL3N5c19yZWdzLmMgYi9hcmNoL2FybTY0L2t2bS9zeXNfcmVn cy5jCmluZGV4IGIxZjc1NTIuLmEwZWU5YjAgMTAwNjQ0Ci0tLSBhL2FyY2gvYXJtNjQva3ZtL3N5 c19yZWdzLmMKKysrIGIvYXJjaC9hcm02NC9rdm0vc3lzX3JlZ3MuYwpAQCAtMjMsNiArMjMsNyBA QAogI2luY2x1ZGUgPGxpbnV4L2JzZWFyY2guaD4KICNpbmNsdWRlIDxsaW51eC9rdm1faG9zdC5o PgogI2luY2x1ZGUgPGxpbnV4L21tLmg+CisjaW5jbHVkZSA8bGludXgvcHJpbnRrLmg+CiAjaW5j bHVkZSA8bGludXgvdWFjY2Vzcy5oPgogCiAjaW5jbHVkZSA8YXNtL2NhY2hlZmx1c2guaD4KQEAg LTg5Nyw4ICs4OTgsMTcgQEAgc3RhdGljIHU2NCByZWFkX2lkX3JlZyhzdHJ1Y3Qgc3lzX3JlZ19k ZXNjIGNvbnN0ICpyLCBib29sIHJheikKIHsKIAl1MzIgaWQgPSBzeXNfcmVnKCh1MzIpci0+T3Aw LCAodTMyKXItPk9wMSwKIAkJCSAodTMyKXItPkNSbiwgKHUzMilyLT5DUm0sICh1MzIpci0+T3Ay KTsKKwl1NjQgdmFsID0gcmF6ID8gMCA6IHJlYWRfc2FuaXRpc2VkX2Z0cl9yZWcoaWQpOwogCi0J cmV0dXJuIHJheiA/IDAgOiByZWFkX3Nhbml0aXNlZF9mdHJfcmVnKGlkKTsKKwlpZiAoaWQgPT0g U1lTX0lEX0FBNjRQRlIwX0VMMSkgeworCQlpZiAodmFsICYgKDB4ZlVMIDw8IElEX0FBNjRQRlIw X1NWRV9TSElGVCkpCisJCQlwcl9lcnJfb25jZSgia3ZtIFslaV06IFNWRSB1bnN1cHBvcnRlZCBm b3IgZ3Vlc3RzLCBzdXBwcmVzc2luZ1xuIiwKKwkJCQkgICAgdGFza19waWRfbnIoY3VycmVudCkp OworCisJCXZhbCAmPSB+KDB4ZlVMIDw8IElEX0FBNjRQRlIwX1NWRV9TSElGVCk7CisJfQorCisJ cmV0dXJuIHZhbDsKIH0KIAogLyogY3B1ZmVhdHVyZSBJRCByZWdpc3RlciBhY2Nlc3MgdHJhcCBo YW5kbGVycyAqLwotLSAKMi4xLjQKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fCmt2bWFybSBtYWlsaW5nIGxpc3QKa3ZtYXJtQGxpc3RzLmNzLmNvbHVtYmlh LmVkdQpodHRwczovL2xpc3RzLmNzLmNvbHVtYmlhLmVkdS9tYWlsbWFuL2xpc3RpbmZvL2t2bWFy bQo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:49168 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932557AbdJJSjq (ORCPT ); Tue, 10 Oct 2017 14:39:46 -0400 From: Dave Martin Subject: [PATCH v3 24/28] arm64/sve: KVM: Hide SVE from CPU features exposed to guests Date: Tue, 10 Oct 2017 19:38:41 +0100 Message-ID: <1507660725-7986-25-git-send-email-Dave.Martin@arm.com> In-Reply-To: <1507660725-7986-1-git-send-email-Dave.Martin@arm.com> References: <1507660725-7986-1-git-send-email-Dave.Martin@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-arch-owner@vger.kernel.org List-ID: To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Ard Biesheuvel , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Szabolcs Nagy , Richard Sandiford , Okamoto Takayuki , kvmarm@lists.cs.columbia.edu, libc-alpha@sourceware.org, linux-arch@vger.kernel.org, Marc Zyngier Message-ID: <20171010183841.Lw9PAExuJ4_WEAcub5Swc_gNFQkwBRXBKr7WeA1GFjM@z> KVM guests cannot currently use SVE, because SVE is always configured to trap to EL2. However, a guest that sees SVE reported as present in ID_AA64PFR0_EL1 may legitimately expect that SVE works and try to use it. Instead of working, the guest will receive an injected undef exception, which may cause the guest to oops or go into a spin. To avoid misleading the guest into believing that SVE will work, this patch masks out the SVE field from ID_AA64PFR0_EL1 when a guest attempts to read this register. No support is explicitly added for ID_AA64ZFR0_EL1 either, so that is still emulated as reading as zero, which is consistent with SVE not being implemented. This is a temporary measure, and will be removed in a later series when full KVM support for SVE is implemented. Signed-off-by: Dave Martin Reviewed-by: Alex Bennée Cc: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b1f7552..a0ee9b0 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -897,8 +898,17 @@ static u64 read_id_reg(struct sys_reg_desc const *r, bool raz) { u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); + u64 val = raz ? 0 : read_sanitised_ftr_reg(id); - return raz ? 0 : read_sanitised_ftr_reg(id); + if (id == SYS_ID_AA64PFR0_EL1) { + if (val & (0xfUL << ID_AA64PFR0_SVE_SHIFT)) + pr_err_once("kvm [%i]: SVE unsupported for guests, suppressing\n", + task_pid_nr(current)); + + val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); + } + + return val; } /* cpufeature ID register access trap handlers */ -- 2.1.4