From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chintan Pandya Subject: [PATCH v5 2/4] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable Date: Tue, 27 Mar 2018 18:54:58 +0530 Message-ID: <1522157100-16879-3-git-send-email-cpandya@codeaurora.org> References: <1522157100-16879-1-git-send-email-cpandya@codeaurora.org> Return-path: In-Reply-To: <1522157100-16879-1-git-send-email-cpandya@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, toshi.kani@hpe.com Cc: arnd@arndb.de, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, james.morse@arm.com, kristina.martsenko@arm.com, takahiro.akashi@linaro.org, gregkh@linuxfoundation.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, akpm@linux-foundation.org, Chintan Pandya List-Id: linux-arch.vger.kernel.org Add an interface to invalidate intermediate page tables from TLB for kernel. Signed-off-by: Chintan Pandya --- Introduced in v5 arch/arm64/include/asm/tlbflush.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 9e82dd7..6a4816d 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -209,6 +209,12 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, dsb(ish); } +static inline void __flush_tlb_kernel_pgtable(unsigned long addr) +{ + addr >>= 12; + __tlbi(vaae1is, addr); + dsb(ish); +} #endif #endif -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.codeaurora.org ([198.145.29.96]:33738 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752841AbeC0NZc (ORCPT ); Tue, 27 Mar 2018 09:25:32 -0400 From: Chintan Pandya Subject: [PATCH v5 2/4] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable Date: Tue, 27 Mar 2018 18:54:58 +0530 Message-ID: <1522157100-16879-3-git-send-email-cpandya@codeaurora.org> In-Reply-To: <1522157100-16879-1-git-send-email-cpandya@codeaurora.org> References: <1522157100-16879-1-git-send-email-cpandya@codeaurora.org> Sender: linux-arch-owner@vger.kernel.org List-ID: To: catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, toshi.kani@hpe.com Cc: arnd@arndb.de, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, james.morse@arm.com, kristina.martsenko@arm.com, takahiro.akashi@linaro.org, gregkh@linuxfoundation.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, akpm@linux-foundation.org, Chintan Pandya Message-ID: <20180327132458.1Lj2V4w2hj8cAt0zTU2ikf-RaeefQiva2nN4LELH1ro@z> Add an interface to invalidate intermediate page tables from TLB for kernel. Signed-off-by: Chintan Pandya --- Introduced in v5 arch/arm64/include/asm/tlbflush.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 9e82dd7..6a4816d 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -209,6 +209,12 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, dsb(ish); } +static inline void __flush_tlb_kernel_pgtable(unsigned long addr) +{ + addr >>= 12; + __tlbi(vaae1is, addr); + dsb(ish); +} #endif #endif -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project