From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chintan Pandya Subject: [PATCH v9 2/4] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable Date: Mon, 30 Apr 2018 13:11:32 +0530 Message-ID: <1525074094-25839-3-git-send-email-cpandya@codeaurora.org> References: <1525074094-25839-1-git-send-email-cpandya@codeaurora.org> Return-path: In-Reply-To: <1525074094-25839-1-git-send-email-cpandya@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Will Deacon , Arnd Bergmann , Mark Rutland , Ard Biesheuvel , Marc Zyngier , Andrew Morton Cc: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Philip Elcan , James Morse , Kristina Martsenko , Toshi Kani , Dave Hansen , Vitaly Kuznetsov , Joerg Roedel , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, Chintan Pandya List-Id: linux-arch.vger.kernel.org Add an interface to invalidate intermediate page tables from TLB for kernel. Signed-off-by: Chintan Pandya --- arch/arm64/include/asm/tlbflush.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index dfc61d7..a4a1901 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -218,6 +218,13 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, dsb(ish); } +static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) +{ + unsigned long addr = __TLBI_VADDR(kaddr, 0); + + __tlbi(vaae1is, addr); + dsb(ish); +} #endif #endif -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.codeaurora.org ([198.145.29.96]:46518 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751705AbeD3HmO (ORCPT ); Mon, 30 Apr 2018 03:42:14 -0400 From: Chintan Pandya Subject: [PATCH v9 2/4] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable Date: Mon, 30 Apr 2018 13:11:32 +0530 Message-ID: <1525074094-25839-3-git-send-email-cpandya@codeaurora.org> In-Reply-To: <1525074094-25839-1-git-send-email-cpandya@codeaurora.org> References: <1525074094-25839-1-git-send-email-cpandya@codeaurora.org> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Will Deacon , Arnd Bergmann , Mark Rutland , Ard Biesheuvel , Marc Zyngier , Andrew Morton Cc: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Philip Elcan , James Morse , Kristina Martsenko , Toshi Kani , Dave Hansen , Vitaly Kuznetsov , Joerg Roedel , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, Chintan Pandya Message-ID: <20180430074132.Trn5a31FE8xE2pkvTuqVla7_xSZ0ESI_n_vKYcGAM8M@z> Add an interface to invalidate intermediate page tables from TLB for kernel. Signed-off-by: Chintan Pandya --- arch/arm64/include/asm/tlbflush.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index dfc61d7..a4a1901 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -218,6 +218,13 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, dsb(ish); } +static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) +{ + unsigned long addr = __TLBI_VADDR(kaddr, 0); + + __tlbi(vaae1is, addr); + dsb(ish); +} #endif #endif -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project