From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu-cheng Yu Subject: Re: [PATCH 02/10] x86/cet: Introduce WRUSS instruction Date: Thu, 14 Jun 2018 07:43:52 -0700 Message-ID: <1528987432.13101.7.camel@2b52.sc.intel.com> References: <20180607143807.3611-1-yu-cheng.yu@intel.com> <20180607143807.3611-3-yu-cheng.yu@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Balbir Singh Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , "H.J. Lu" , Vedvyas Shanbhogue , "Ravi V. Shankar" , Dave Hansen , Andy Lutomirski , Jonathan Corbet , Oleg Nesterov , Arnd Bergmann , Mike Kravetz List-Id: linux-arch.vger.kernel.org On Thu, 2018-06-14 at 11:30 +1000, Balbir Singh wrote: > On Thu, 2018-06-07 at 07:37 -0700, Yu-cheng Yu wrote: > > WRUSS is a new kernel-mode instruction but writes directly > > to user shadow stack memory. This is used to construct > > a return address on the shadow stack for the signal > > handler. > > > > This instruction can fault if the user shadow stack is > > invalid shadow stack memory. In that case, the kernel does > > fixup. > > > > Signed-off-by: Yu-cheng Yu > > --- > > arch/x86/include/asm/special_insns.h | 44 +++++++++++++++++++++++++++ > > arch/x86/lib/x86-opcode-map.txt | 2 +- > > arch/x86/mm/fault.c | 13 +++++++- > > tools/objtool/arch/x86/lib/x86-opcode-map.txt | 2 +- > > 4 files changed, 58 insertions(+), 3 deletions(-) > > > > diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h > > index 317fc59b512c..8ce532fcc171 100644 > > --- a/arch/x86/include/asm/special_insns.h > > +++ b/arch/x86/include/asm/special_insns.h > > @@ -237,6 +237,50 @@ static inline void clwb(volatile void *__p) > > : [pax] "a" (p)); > > } > > > > +#ifdef CONFIG_X86_INTEL_CET > > + > > +#if defined(CONFIG_IA32_EMULATION) || defined(CONFIG_X86_X32) > > +static inline int write_user_shstk_32(unsigned long addr, unsigned int val) > > +{ > > + int err; > > + > > + asm volatile("1:.byte 0x66, 0x0f, 0x38, 0xf5, 0x37\n" > > It would nice to use something like ASM_WRUSS/Q like ASM_CLAC/ASM_STAC. > Is the 0x37 spurious? I don't see addr/val being used in the instructions > either. > Yes, this is being revised. We are going to require a GCC and binutils that support CET. I will put in the WRUSS instruction, no '.byte' any more. Yu-cheng From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com ([192.55.52.136]:50728 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755092AbeFNOrF (ORCPT ); Thu, 14 Jun 2018 10:47:05 -0400 Message-ID: <1528987432.13101.7.camel@2b52.sc.intel.com> Subject: Re: [PATCH 02/10] x86/cet: Introduce WRUSS instruction From: Yu-cheng Yu Date: Thu, 14 Jun 2018 07:43:52 -0700 In-Reply-To: References: <20180607143807.3611-1-yu-cheng.yu@intel.com> <20180607143807.3611-3-yu-cheng.yu@intel.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-arch-owner@vger.kernel.org List-ID: To: Balbir Singh Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , "H.J. Lu" , Vedvyas Shanbhogue , "Ravi V. Shankar" , Dave Hansen , Andy Lutomirski , Jonathan Corbet , Oleg Nesterov , Arnd Bergmann , Mike Kravetz Message-ID: <20180614144352.kJpq9dk6UzDm9e_p-RbiZKq22lPF3cDjOnbOadfd93w@z> On Thu, 2018-06-14 at 11:30 +1000, Balbir Singh wrote: > On Thu, 2018-06-07 at 07:37 -0700, Yu-cheng Yu wrote: > > WRUSS is a new kernel-mode instruction but writes directly > > to user shadow stack memory. This is used to construct > > a return address on the shadow stack for the signal > > handler. > > > > This instruction can fault if the user shadow stack is > > invalid shadow stack memory. In that case, the kernel does > > fixup. > > > > Signed-off-by: Yu-cheng Yu > > --- > > arch/x86/include/asm/special_insns.h | 44 +++++++++++++++++++++++++++ > > arch/x86/lib/x86-opcode-map.txt | 2 +- > > arch/x86/mm/fault.c | 13 +++++++- > > tools/objtool/arch/x86/lib/x86-opcode-map.txt | 2 +- > > 4 files changed, 58 insertions(+), 3 deletions(-) > > > > diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h > > index 317fc59b512c..8ce532fcc171 100644 > > --- a/arch/x86/include/asm/special_insns.h > > +++ b/arch/x86/include/asm/special_insns.h > > @@ -237,6 +237,50 @@ static inline void clwb(volatile void *__p) > > : [pax] "a" (p)); > > } > > > > +#ifdef CONFIG_X86_INTEL_CET > > + > > +#if defined(CONFIG_IA32_EMULATION) || defined(CONFIG_X86_X32) > > +static inline int write_user_shstk_32(unsigned long addr, unsigned int val) > > +{ > > + int err; > > + > > + asm volatile("1:.byte 0x66, 0x0f, 0x38, 0xf5, 0x37\n" > > It would nice to use something like ASM_WRUSS/Q like ASM_CLAC/ASM_STAC. > Is the 0x37 spurious? I don't see addr/val being used in the instructions > either. > Yes, this is being revised. We are going to require a GCC and binutils that support CET. I will put in the WRUSS instruction, no '.byte' any more. Yu-cheng