From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pu Wen Subject: [PATCH v2 09/17] x86/bugs: add lfence mitigation to spectre v2 and no meltdown for Hygon Date: Mon, 23 Jul 2018 21:20:29 +0800 Message-ID: <1532352037-7151-10-git-send-email-puwen@hygon.cn> References: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-arch@vger.kernel.org, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org List-Id: linux-arch.vger.kernel.org VG8gc2hhcmUgY29kZXMgYmV0d2VlbiBBTUQgYW5kIEh5Z29uIHRvIG1pdGlnYXRlIFNwZWN0cmUg VjIgUmV0cG9saW5lCnZ1bG5lcmFiaWxpdHksIHJlbmFtZSBtYWNyb3MgU1BFQ1RSRV9WMl9SRVRQ T0xJTkVfTUlOSU1BTF9BTUQgdG8KU1BFQ1RSRV9WMl9SRVRQT0xJTkVfTUlOSU1BTF9MRkVOQ0Us IGFuZCBTUEVDVFJFX1YyX0NNRF9SRVRQT0xJTkVfQU1ECnRvIFNQRUNUUkVfVjJfQ01EX1JFVFBP TElORV9MRkVOQ0UuCgpBcyBIeWdvbiBwcm9jZXNzb3JzIGlzIG5vdCBhZmZlY3RlZCBieSBtZWx0 ZG93biB2dWxuZXJhYmlsaXR5IGFzIEFNRCdzLApzbyBhZGQgZXhjZXB0aW9uIGluIGFycmF5IGNw dV9ub19tZWx0ZG93bltdIGZvciBpdC4KClNpZ25lZC1vZmYtYnk6IFB1IFdlbiA8cHV3ZW5AaHln b24uY24+Ci0tLQogYXJjaC94ODYvaW5jbHVkZS9hc20vbm9zcGVjLWJyYW5jaC5oIHwgIDQgKyst LQogYXJjaC94ODYva2VybmVsL2NwdS9idWdzLmMgICAgICAgICAgIHwgMjggKysrKysrKysrKysr KysrLS0tLS0tLS0tLS0tLQogYXJjaC94ODYva2VybmVsL2NwdS9jb21tb24uYyAgICAgICAgIHwg IDEgKwogMyBmaWxlcyBjaGFuZ2VkLCAxOCBpbnNlcnRpb25zKCspLCAxNSBkZWxldGlvbnMoLSkK CmRpZmYgLS1naXQgYS9hcmNoL3g4Ni9pbmNsdWRlL2FzbS9ub3NwZWMtYnJhbmNoLmggYi9hcmNo L3g4Ni9pbmNsdWRlL2FzbS9ub3NwZWMtYnJhbmNoLmgKaW5kZXggZjZmNmM2My4uYWFkNmI5YyAx MDA2NDQKLS0tIGEvYXJjaC94ODYvaW5jbHVkZS9hc20vbm9zcGVjLWJyYW5jaC5oCisrKyBiL2Fy Y2gveDg2L2luY2x1ZGUvYXNtL25vc3BlYy1icmFuY2guaApAQCAtMjExLDkgKzIxMSw5IEBACiBl bnVtIHNwZWN0cmVfdjJfbWl0aWdhdGlvbiB7CiAJU1BFQ1RSRV9WMl9OT05FLAogCVNQRUNUUkVf VjJfUkVUUE9MSU5FX01JTklNQUwsCi0JU1BFQ1RSRV9WMl9SRVRQT0xJTkVfTUlOSU1BTF9BTUQs CisJU1BFQ1RSRV9WMl9SRVRQT0xJTkVfTUlOSU1BTF9MRkVOQ0UsCiAJU1BFQ1RSRV9WMl9SRVRQ T0xJTkVfR0VORVJJQywKLQlTUEVDVFJFX1YyX1JFVFBPTElORV9BTUQsCisJU1BFQ1RSRV9WMl9S RVRQT0xJTkVfTEZFTkNFLAogCVNQRUNUUkVfVjJfSUJSUywKIH07CiAKZGlmZiAtLWdpdCBhL2Fy Y2gveDg2L2tlcm5lbC9jcHUvYnVncy5jIGIvYXJjaC94ODYva2VybmVsL2NwdS9idWdzLmMKaW5k ZXggNWMwZWEzOS4uNWQwYmE2MSAxMDA2NDQKLS0tIGEvYXJjaC94ODYva2VybmVsL2NwdS9idWdz LmMKKysrIGIvYXJjaC94ODYva2VybmVsL2NwdS9idWdzLmMKQEAgLTEyMSwxNSArMTIxLDE1IEBA IGVudW0gc3BlY3RyZV92Ml9taXRpZ2F0aW9uX2NtZCB7CiAJU1BFQ1RSRV9WMl9DTURfRk9SQ0Us CiAJU1BFQ1RSRV9WMl9DTURfUkVUUE9MSU5FLAogCVNQRUNUUkVfVjJfQ01EX1JFVFBPTElORV9H RU5FUklDLAotCVNQRUNUUkVfVjJfQ01EX1JFVFBPTElORV9BTUQsCisJU1BFQ1RSRV9WMl9DTURf UkVUUE9MSU5FX0xGRU5DRSwKIH07CiAKIHN0YXRpYyBjb25zdCBjaGFyICpzcGVjdHJlX3YyX3N0 cmluZ3NbXSA9IHsKIAlbU1BFQ1RSRV9WMl9OT05FXQkJCT0gIlZ1bG5lcmFibGUiLAogCVtTUEVD VFJFX1YyX1JFVFBPTElORV9NSU5JTUFMXQkJPSAiVnVsbmVyYWJsZTogTWluaW1hbCBnZW5lcmlj IEFTTSByZXRwb2xpbmUiLAotCVtTUEVDVFJFX1YyX1JFVFBPTElORV9NSU5JTUFMX0FNRF0JPSAi VnVsbmVyYWJsZTogTWluaW1hbCBBTUQgQVNNIHJldHBvbGluZSIsCisJW1NQRUNUUkVfVjJfUkVU UE9MSU5FX01JTklNQUxfTEZFTkNFXQk9ICJWdWxuZXJhYmxlOiBNaW5pbWFsIExGRU5DRSBBU00g cmV0cG9saW5lIiwKIAlbU1BFQ1RSRV9WMl9SRVRQT0xJTkVfR0VORVJJQ10JCT0gIk1pdGlnYXRp b246IEZ1bGwgZ2VuZXJpYyByZXRwb2xpbmUiLAotCVtTUEVDVFJFX1YyX1JFVFBPTElORV9BTURd CQk9ICJNaXRpZ2F0aW9uOiBGdWxsIEFNRCByZXRwb2xpbmUiLAorCVtTUEVDVFJFX1YyX1JFVFBP TElORV9MRkVOQ0VdCQk9ICJNaXRpZ2F0aW9uOiBGdWxsIExGRU5DRSByZXRwb2xpbmUiLAogfTsK IAogI3VuZGVmIHByX2ZtdApAQCAtMjYwLDcgKzI2MCw3IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3Qg ewogCXsgIm9mZiIsICAgICAgICAgICAgICAgU1BFQ1RSRV9WMl9DTURfTk9ORSwgICAgICAgICAg ICAgIGZhbHNlIH0sCiAJeyAib24iLCAgICAgICAgICAgICAgICBTUEVDVFJFX1YyX0NNRF9GT1JD RSwgICAgICAgICAgICAgdHJ1ZSB9LAogCXsgInJldHBvbGluZSIsICAgICAgICAgU1BFQ1RSRV9W Ml9DTURfUkVUUE9MSU5FLCAgICAgICAgIGZhbHNlIH0sCi0JeyAicmV0cG9saW5lLGFtZCIsICAg ICBTUEVDVFJFX1YyX0NNRF9SRVRQT0xJTkVfQU1ELCAgICAgZmFsc2UgfSwKKwl7ICJyZXRwb2xp bmUsbGZlbmNlIiwgICAgIFNQRUNUUkVfVjJfQ01EX1JFVFBPTElORV9MRkVOQ0UsICAgICBmYWxz ZSB9LAogCXsgInJldHBvbGluZSxnZW5lcmljIiwgU1BFQ1RSRV9WMl9DTURfUkVUUE9MSU5FX0dF TkVSSUMsIGZhbHNlIH0sCiAJeyAiYXV0byIsICAgICAgICAgICAgICBTUEVDVFJFX1YyX0NNRF9B VVRPLCAgICAgICAgICAgICAgZmFsc2UgfSwKIH07CkBAIC0yOTIsMTYgKzI5MiwxNyBAQCBzdGF0 aWMgZW51bSBzcGVjdHJlX3YyX21pdGlnYXRpb25fY21kIF9faW5pdCBzcGVjdHJlX3YyX3BhcnNl X2NtZGxpbmUodm9pZCkKIAl9CiAKIAlpZiAoKGNtZCA9PSBTUEVDVFJFX1YyX0NNRF9SRVRQT0xJ TkUgfHwKLQkgICAgIGNtZCA9PSBTUEVDVFJFX1YyX0NNRF9SRVRQT0xJTkVfQU1EIHx8CisJICAg ICBjbWQgPT0gU1BFQ1RSRV9WMl9DTURfUkVUUE9MSU5FX0xGRU5DRSB8fAogCSAgICAgY21kID09 IFNQRUNUUkVfVjJfQ01EX1JFVFBPTElORV9HRU5FUklDKSAmJgogCSAgICAhSVNfRU5BQkxFRChD T05GSUdfUkVUUE9MSU5FKSkgewogCQlwcl9lcnIoIiVzIHNlbGVjdGVkIGJ1dCBub3QgY29tcGls ZWQgaW4uIFN3aXRjaGluZyB0byBBVVRPIHNlbGVjdFxuIiwgbWl0aWdhdGlvbl9vcHRpb25zW2ld Lm9wdGlvbik7CiAJCXJldHVybiBTUEVDVFJFX1YyX0NNRF9BVVRPOwogCX0KIAotCWlmIChjbWQg PT0gU1BFQ1RSRV9WMl9DTURfUkVUUE9MSU5FX0FNRCAmJgorCWlmIChjbWQgPT0gU1BFQ1RSRV9W Ml9DTURfUkVUUE9MSU5FX0xGRU5DRSAmJgorCSAgICBib290X2NwdV9kYXRhLng4Nl92ZW5kb3Ig IT0gWDg2X1ZFTkRPUl9IWUdPTiAmJgogCSAgICBib290X2NwdV9kYXRhLng4Nl92ZW5kb3IgIT0g WDg2X1ZFTkRPUl9BTUQpIHsKLQkJcHJfZXJyKCJyZXRwb2xpbmUsYW1kIHNlbGVjdGVkIGJ1dCBD UFUgaXMgbm90IEFNRC4gU3dpdGNoaW5nIHRvIEFVVE8gc2VsZWN0XG4iKTsKKwkJcHJfZXJyKCJy ZXRwb2xpbmUsYW1kIHNlbGVjdGVkIGJ1dCBDUFUgaXMgbm90IEFNRCBvciBIeWdvbi4gU3dpdGNo aW5nIHRvIEFVVE8gc2VsZWN0XG4iKTsKIAkJcmV0dXJuIFNQRUNUUkVfVjJfQ01EX0FVVE87CiAJ fQogCkBAIC0zNTIsOSArMzUzLDkgQEAgc3RhdGljIHZvaWQgX19pbml0IHNwZWN0cmVfdjJfc2Vs ZWN0X21pdGlnYXRpb24odm9pZCkKIAkJaWYgKElTX0VOQUJMRUQoQ09ORklHX1JFVFBPTElORSkp CiAJCQlnb3RvIHJldHBvbGluZV9hdXRvOwogCQlicmVhazsKLQljYXNlIFNQRUNUUkVfVjJfQ01E X1JFVFBPTElORV9BTUQ6CisJY2FzZSBTUEVDVFJFX1YyX0NNRF9SRVRQT0xJTkVfTEZFTkNFOgog CQlpZiAoSVNfRU5BQkxFRChDT05GSUdfUkVUUE9MSU5FKSkKLQkJCWdvdG8gcmV0cG9saW5lX2Ft ZDsKKwkJCWdvdG8gcmV0cG9saW5lX2xmZW5jZTsKIAkJYnJlYWs7CiAJY2FzZSBTUEVDVFJFX1Yy X0NNRF9SRVRQT0xJTkVfR0VORVJJQzoKIAkJaWYgKElTX0VOQUJMRUQoQ09ORklHX1JFVFBPTElO RSkpCkBAIC0zNjksMTQgKzM3MCwxNSBAQCBzdGF0aWMgdm9pZCBfX2luaXQgc3BlY3RyZV92Ml9z ZWxlY3RfbWl0aWdhdGlvbih2b2lkKQogCXJldHVybjsKIAogcmV0cG9saW5lX2F1dG86Ci0JaWYg KGJvb3RfY3B1X2RhdGEueDg2X3ZlbmRvciA9PSBYODZfVkVORE9SX0FNRCkgewotCXJldHBvbGlu ZV9hbWQ6CisJaWYgKGJvb3RfY3B1X2RhdGEueDg2X3ZlbmRvciA9PSBYODZfVkVORE9SX0FNRCB8 fAorCSAgICBib290X2NwdV9kYXRhLng4Nl92ZW5kb3IgPT0gWDg2X1ZFTkRPUl9IWUdPTikgewor CXJldHBvbGluZV9sZmVuY2U6CiAJCWlmICghYm9vdF9jcHVfaGFzKFg4Nl9GRUFUVVJFX0xGRU5D RV9SRFRTQykpIHsKIAkJCXByX2VycigiU3BlY3RyZSBtaXRpZ2F0aW9uOiBMRkVOQ0Ugbm90IHNl cmlhbGl6aW5nLCBzd2l0Y2hpbmcgdG8gZ2VuZXJpYyByZXRwb2xpbmVcbiIpOwogCQkJZ290byBy ZXRwb2xpbmVfZ2VuZXJpYzsKIAkJfQotCQltb2RlID0gcmV0cF9jb21waWxlcigpID8gU1BFQ1RS RV9WMl9SRVRQT0xJTkVfQU1EIDoKLQkJCQkJIFNQRUNUUkVfVjJfUkVUUE9MSU5FX01JTklNQUxf QU1EOworCQltb2RlID0gcmV0cF9jb21waWxlcigpID8gU1BFQ1RSRV9WMl9SRVRQT0xJTkVfTEZF TkNFIDoKKwkJCQkJIFNQRUNUUkVfVjJfUkVUUE9MSU5FX01JTklNQUxfTEZFTkNFOwogCQlzZXR1 cF9mb3JjZV9jcHVfY2FwKFg4Nl9GRUFUVVJFX1JFVFBPTElORV9BTUQpOwogCQlzZXR1cF9mb3Jj ZV9jcHVfY2FwKFg4Nl9GRUFUVVJFX1JFVFBPTElORSk7CiAJfSBlbHNlIHsKZGlmZiAtLWdpdCBh L2FyY2gveDg2L2tlcm5lbC9jcHUvY29tbW9uLmMgYi9hcmNoL3g4Ni9rZXJuZWwvY3B1L2NvbW1v bi5jCmluZGV4IGViNGNiM2UuLjA2YjMxNjggMTAwNjQ0Ci0tLSBhL2FyY2gveDg2L2tlcm5lbC9j cHUvY29tbW9uLmMKKysrIGIvYXJjaC94ODYva2VybmVsL2NwdS9jb21tb24uYwpAQCAtOTY4LDYg Kzk2OCw3IEBAIHN0YXRpYyBjb25zdCBfX2luaXRjb25zdCBzdHJ1Y3QgeDg2X2NwdV9pZCBjcHVf bm9fc3BlY3VsYXRpb25bXSA9IHsKIAogc3RhdGljIGNvbnN0IF9faW5pdGNvbnN0IHN0cnVjdCB4 ODZfY3B1X2lkIGNwdV9ub19tZWx0ZG93bltdID0gewogCXsgWDg2X1ZFTkRPUl9BTUQgfSwKKwl7 IFg4Nl9WRU5ET1JfSFlHT04gfSwKIAl7fQogfTsKIAotLSAKMi43LjQKCgpfX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpYZW4tZGV2ZWwgbWFpbGluZyBsaXN0 Clhlbi1kZXZlbEBsaXN0cy54ZW5wcm9qZWN0Lm9yZwpodHRwczovL2xpc3RzLnhlbnByb2plY3Qu b3JnL21haWxtYW4vbGlzdGluZm8veGVuLWRldmVs From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp21.cstnet.cn ([159.226.251.21]:52028 "EHLO cstnet.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388087AbeGWO3f (ORCPT ); Mon, 23 Jul 2018 10:29:35 -0400 From: Pu Wen Subject: [PATCH v2 09/17] x86/bugs: add lfence mitigation to spectre v2 and no meltdown for Hygon Date: Mon, 23 Jul 2018 21:20:29 +0800 Message-ID: <1532352037-7151-10-git-send-email-puwen@hygon.cn> In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> References: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Sender: linux-arch-owner@vger.kernel.org List-ID: To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, kvm@vger.kernel.org, xen-devel@lists.xenproject.org Message-ID: <20180723132029.S4tGfb2ZXmHVcHsoSACw3oaTwjucXZ2FFz4W8DgO5KE@z> To share codes between AMD and Hygon to mitigate Spectre V2 Retpoline vulnerability, rename macros SPECTRE_V2_RETPOLINE_MINIMAL_AMD to SPECTRE_V2_RETPOLINE_MINIMAL_LFENCE, and SPECTRE_V2_CMD_RETPOLINE_AMD to SPECTRE_V2_CMD_RETPOLINE_LFENCE. As Hygon processors is not affected by meltdown vulnerability as AMD's, so add exception in array cpu_no_meltdown[] for it. Signed-off-by: Pu Wen --- arch/x86/include/asm/nospec-branch.h | 4 ++-- arch/x86/kernel/cpu/bugs.c | 28 +++++++++++++++------------- arch/x86/kernel/cpu/common.c | 1 + 3 files changed, 18 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index f6f6c63..aad6b9c 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -211,9 +211,9 @@ enum spectre_v2_mitigation { SPECTRE_V2_NONE, SPECTRE_V2_RETPOLINE_MINIMAL, - SPECTRE_V2_RETPOLINE_MINIMAL_AMD, + SPECTRE_V2_RETPOLINE_MINIMAL_LFENCE, SPECTRE_V2_RETPOLINE_GENERIC, - SPECTRE_V2_RETPOLINE_AMD, + SPECTRE_V2_RETPOLINE_LFENCE, SPECTRE_V2_IBRS, }; diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 5c0ea39..5d0ba61 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -121,15 +121,15 @@ enum spectre_v2_mitigation_cmd { SPECTRE_V2_CMD_FORCE, SPECTRE_V2_CMD_RETPOLINE, SPECTRE_V2_CMD_RETPOLINE_GENERIC, - SPECTRE_V2_CMD_RETPOLINE_AMD, + SPECTRE_V2_CMD_RETPOLINE_LFENCE, }; static const char *spectre_v2_strings[] = { [SPECTRE_V2_NONE] = "Vulnerable", [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", - [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", + [SPECTRE_V2_RETPOLINE_MINIMAL_LFENCE] = "Vulnerable: Minimal LFENCE ASM retpoline", [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", - [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", + [SPECTRE_V2_RETPOLINE_LFENCE] = "Mitigation: Full LFENCE retpoline", }; #undef pr_fmt @@ -260,7 +260,7 @@ static const struct { { "off", SPECTRE_V2_CMD_NONE, false }, { "on", SPECTRE_V2_CMD_FORCE, true }, { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, - { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, + { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, { "auto", SPECTRE_V2_CMD_AUTO, false }, }; @@ -292,16 +292,17 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) } if ((cmd == SPECTRE_V2_CMD_RETPOLINE || - cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || + cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && !IS_ENABLED(CONFIG_RETPOLINE)) { pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); return SPECTRE_V2_CMD_AUTO; } - if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && + if (cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE && + boot_cpu_data.x86_vendor != X86_VENDOR_HYGON && boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { - pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); + pr_err("retpoline,amd selected but CPU is not AMD or Hygon. Switching to AUTO select\n"); return SPECTRE_V2_CMD_AUTO; } @@ -352,9 +353,9 @@ static void __init spectre_v2_select_mitigation(void) if (IS_ENABLED(CONFIG_RETPOLINE)) goto retpoline_auto; break; - case SPECTRE_V2_CMD_RETPOLINE_AMD: + case SPECTRE_V2_CMD_RETPOLINE_LFENCE: if (IS_ENABLED(CONFIG_RETPOLINE)) - goto retpoline_amd; + goto retpoline_lfence; break; case SPECTRE_V2_CMD_RETPOLINE_GENERIC: if (IS_ENABLED(CONFIG_RETPOLINE)) @@ -369,14 +370,15 @@ static void __init spectre_v2_select_mitigation(void) return; retpoline_auto: - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { - retpoline_amd: + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { + retpoline_lfence: if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); goto retpoline_generic; } - mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : - SPECTRE_V2_RETPOLINE_MINIMAL_AMD; + mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_LFENCE : + SPECTRE_V2_RETPOLINE_MINIMAL_LFENCE; setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); setup_force_cpu_cap(X86_FEATURE_RETPOLINE); } else { diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index eb4cb3e..06b3168 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -968,6 +968,7 @@ static const __initconst struct x86_cpu_id cpu_no_speculation[] = { static const __initconst struct x86_cpu_id cpu_no_meltdown[] = { { X86_VENDOR_AMD }, + { X86_VENDOR_HYGON }, {} }; -- 2.7.4