From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pu Wen Subject: [PATCH v2 01/17] x86/cpu: create Dhyana init file and register new cpu_dev to system Date: Mon, 23 Jul 2018 21:20:21 +0800 Message-ID: <1532352037-7151-2-git-send-email-puwen@hygon.cn> References: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-arch@vger.kernel.org, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org List-Id: linux-arch.vger.kernel.org QWRkIHg4NiBhcmNoaXRlY3R1cmUgc3VwcG9ydCBmb3IgbmV3IHByb2Nlc3NvciBIeWdvbiBEaHlh bmEgRmFtaWx5IDE4aC4KUmV3b3JrIHRvIGNyZWF0ZSBhIHNlcGFyYXRlZCBmaWxlKGFyY2gveDg2 L2tlcm5lbC9jcHUvaHlnb24uYykgZnJvbSB0aGUKQU1EIGluaXQgb25lKGFyY2gveDg2L2tlcm5l bC9jcHUvYW1kLmMpIHRvIGluaXRpYWxpemUgRGh5YW5hIENQVS4gSW4KdGhpcyB3YXkgd2UgY2Fu IHJlbW92ZSBvbGQgQU1EIGFyY2hpdGVjdHVyZSBzdXBwb3J0IGNvZGVzIGZyb20gSHlnb24KY29k ZSBwYXRoIGFuZCBnZW5lcmF0ZSBhIGNsZWFyIGluaXRpYWxpemF0aW9uIGZsb3cgZm9yIEh5Z29u IHByb2Nlc3NvcnMsCml0IGFsc28gcmVkdWNlIGxvbmctdGVybSBtYWludGVuYW5jZSBlZmZvcnQu CkFsc28gYWRkIGh5Z29uLmMgTWFpbnRhaW5lciBpbmZvcm1hdGlvbiBpbiBhY2NvcmRhbmNlLgoK VG8gaWRlbnRpZnkgSHlnb24gcHJvY2Vzc29ycywgYWRkIGEgbmV3IHZlbmRvciB0eXBlIFg4Nl9W RU5ET1JfSFlHT04oOSkKZm9yIHN5c3RlbSByZWNvZ25pdGlvbi4KClRvIGVuYWJsZSBIeWdvbiBw cm9jZXNzb3IgY29uZmlnLCBhZGQgYSBzZXBhcmF0ZWQgS2NvbmZpZyBlbnRyeShDUFVfU1VQXwpI WUdPTikgZm9yIERoeWFuYSBDUFUgaW4ga2VybmVsIGNvbmZpZyBzZXR1cC4KClNpZ25lZC1vZmYt Ynk6IFB1IFdlbiA8cHV3ZW5AaHlnb24uY24+Ci0tLQogTUFJTlRBSU5FUlMgICAgICAgICAgICAg ICAgICAgICAgfCAgIDYgKwogYXJjaC94ODYvS2NvbmZpZy5jcHUgICAgICAgICAgICAgfCAgMTMg KysKIGFyY2gveDg2L2luY2x1ZGUvYXNtL3Byb2Nlc3Nvci5oIHwgICAzICstCiBhcmNoL3g4Ni9r ZXJuZWwvY3B1L01ha2VmaWxlICAgICB8ICAgMSArCiBhcmNoL3g4Ni9rZXJuZWwvY3B1L2h5Z29u LmMgICAgICB8IDQwMSArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysKIDUg ZmlsZXMgY2hhbmdlZCwgNDIzIGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkKIGNyZWF0ZSBt b2RlIDEwMDY0NCBhcmNoL3g4Ni9rZXJuZWwvY3B1L2h5Z29uLmMKCmRpZmYgLS1naXQgYS9NQUlO VEFJTkVSUyBiL01BSU5UQUlORVJTCmluZGV4IDBmZTQyMjguLmFkZTM5ZjIgMTAwNjQ0Ci0tLSBh L01BSU5UQUlORVJTCisrKyBiL01BSU5UQUlORVJTCkBAIC02NjA0LDYgKzY2MDQsMTIgQEAgUzoJ TWFpbnRhaW5lZAogRjoJbW0vbWVtb3J5LWZhaWx1cmUuYwogRjoJbW0vaHdwb2lzb24taW5qZWN0 LmMKIAorSFlHT04gUFJPQ0VTU09SIFNVUFBPUlQKK006CVB1IFdlbiA8cHV3ZW5AaHlnb24uY24+ CitMOglsaW51eC1hcmNoQHZnZXIua2VybmVsLm9yZworUzoJU3VwcG9ydGVkCitGOglhcmNoL3g4 Ni9rZXJuZWwvY3B1L2h5Z29uLmMKKwogSHlwZXItViBDT1JFIEFORCBEUklWRVJTCiBNOgkiSy4g WS4gU3Jpbml2YXNhbiIgPGt5c0BtaWNyb3NvZnQuY29tPgogTToJSGFpeWFuZyBaaGFuZyA8aGFp eWFuZ3pAbWljcm9zb2Z0LmNvbT4KZGlmZiAtLWdpdCBhL2FyY2gveDg2L0tjb25maWcuY3B1IGIv YXJjaC94ODYvS2NvbmZpZy5jcHUKaW5kZXggNjM4NDExZi4uMmU5MjI2NyAxMDA2NDQKLS0tIGEv YXJjaC94ODYvS2NvbmZpZy5jcHUKKysrIGIvYXJjaC94ODYvS2NvbmZpZy5jcHUKQEAgLTQyNiw2 ICs0MjYsMTkgQEAgY29uZmlnIENQVV9TVVBfQU1ECiAKIAkgIElmIHVuc3VyZSwgc2F5IE4uCiAK K2NvbmZpZyBDUFVfU1VQX0hZR09OCisJZGVmYXVsdCB5CisJYm9vbCAiU3VwcG9ydCBIeWdvbiBw cm9jZXNzb3JzIiBpZiBQUk9DRVNTT1JfU0VMRUNUCisJaGVscAorCSAgVGhpcyBlbmFibGVzIGRl dGVjdGlvbiwgdHVuaW5ncyBhbmQgcXVpcmtzIGZvciBIeWdvbiBwcm9jZXNzb3JzCisKKwkgIFlv dSBuZWVkIHRoaXMgZW5hYmxlZCBpZiB5b3Ugd2FudCB5b3VyIGtlcm5lbCB0byBydW4gb24gYW4K KwkgIEh5Z29uIENQVS4gRGlzYWJsaW5nIHRoaXMgb3B0aW9uIG9uIG90aGVyIHR5cGVzIG9mIENQ VXMKKwkgIG1ha2VzIHRoZSBrZXJuZWwgYSB0aW55IGJpdCBzbWFsbGVyLiBEaXNhYmxpbmcgaXQg b24gYW4gSHlnb24KKwkgIENQVSBtaWdodCByZW5kZXIgdGhlIGtlcm5lbCB1bmJvb3RhYmxlLgor CisJICBJZiB1bnN1cmUsIHNheSBOLgorCiBjb25maWcgQ1BVX1NVUF9DRU5UQVVSCiAJZGVmYXVs dCB5CiAJYm9vbCAiU3VwcG9ydCBDZW50YXVyIHByb2Nlc3NvcnMiIGlmIFBST0NFU1NPUl9TRUxF Q1QKZGlmZiAtLWdpdCBhL2FyY2gveDg2L2luY2x1ZGUvYXNtL3Byb2Nlc3Nvci5oIGIvYXJjaC94 ODYvaW5jbHVkZS9hc20vcHJvY2Vzc29yLmgKaW5kZXggY2ZkMjllZS4uYjRmNGZiZCAxMDA2NDQK LS0tIGEvYXJjaC94ODYvaW5jbHVkZS9hc20vcHJvY2Vzc29yLmgKKysrIGIvYXJjaC94ODYvaW5j bHVkZS9hc20vcHJvY2Vzc29yLmgKQEAgLTE1Myw3ICsxNTMsOCBAQCBlbnVtIGNwdWlkX3JlZ3Nf aWR4IHsKICNkZWZpbmUgWDg2X1ZFTkRPUl9DRU5UQVVSCTUKICNkZWZpbmUgWDg2X1ZFTkRPUl9U UkFOU01FVEEJNwogI2RlZmluZSBYODZfVkVORE9SX05TQwkJOAotI2RlZmluZSBYODZfVkVORE9S X05VTQkJOQorI2RlZmluZSBYODZfVkVORE9SX0hZR09OCTkKKyNkZWZpbmUgWDg2X1ZFTkRPUl9O VU0JCTEwCiAKICNkZWZpbmUgWDg2X1ZFTkRPUl9VTktOT1dOCTB4ZmYKIApkaWZmIC0tZ2l0IGEv YXJjaC94ODYva2VybmVsL2NwdS9NYWtlZmlsZSBiL2FyY2gveDg2L2tlcm5lbC9jcHUvTWFrZWZp bGUKaW5kZXggN2E0MDE5Ni4uODg5Y2U1OCAxMDA2NDQKLS0tIGEvYXJjaC94ODYva2VybmVsL2Nw dS9NYWtlZmlsZQorKysgYi9hcmNoL3g4Ni9rZXJuZWwvY3B1L01ha2VmaWxlCkBAIC0zMCw2ICsz MCw3IEBAIG9iai0kKENPTkZJR19YODZfRkVBVFVSRV9OQU1FUykgKz0gY2FwZmxhZ3MubyBwb3dl cmZsYWdzLm8KIAogb2JqLSQoQ09ORklHX0NQVV9TVVBfSU5URUwpCQkrPSBpbnRlbC5vIGludGVs X3Bjb25maWcubwogb2JqLSQoQ09ORklHX0NQVV9TVVBfQU1EKQkJKz0gYW1kLm8KK29iai0kKENP TkZJR19DUFVfU1VQX0hZR09OKQkJKz0gaHlnb24ubwogb2JqLSQoQ09ORklHX0NQVV9TVVBfQ1lS SVhfMzIpCQkrPSBjeXJpeC5vCiBvYmotJChDT05GSUdfQ1BVX1NVUF9DRU5UQVVSKQkJKz0gY2Vu dGF1ci5vCiBvYmotJChDT05GSUdfQ1BVX1NVUF9UUkFOU01FVEFfMzIpCSs9IHRyYW5zbWV0YS5v CmRpZmYgLS1naXQgYS9hcmNoL3g4Ni9rZXJuZWwvY3B1L2h5Z29uLmMgYi9hcmNoL3g4Ni9rZXJu ZWwvY3B1L2h5Z29uLmMKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMC4uY2MyOTZl NQotLS0gL2Rldi9udWxsCisrKyBiL2FyY2gveDg2L2tlcm5lbC9jcHUvaHlnb24uYwpAQCAtMCww ICsxLDQwMSBAQAorLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjArCisvKgorICog SHlnb24gUHJvY2Vzc29yIFN1cHBvcnQgZm9yIExpbnV4CisgKgorICogQ29weXJpZ2h0IChjKSBD aGVuZ2R1IEhhaWd1YW5nIElDIERlc2lnbiBDby4sIEx0ZC4KKyAqCisgKiBBdXRob3I6IDIwMTgg UHUgV2VuIDxwdXdlbkBoeWdvbi5jbj4KKyAqCisgKiBUaGlzIGZpbGUgaXMgbGljZW5zZWQgdW5k ZXIgdGhlIHRlcm1zIG9mIHRoZSBHTlUgR2VuZXJhbAorICogTGljZW5zZSB2Mi4wIG9yIGxhdGVy LiBTZWUgZmlsZSBDT1BZSU5HIGZvciBkZXRhaWxzLgorICovCisjaW5jbHVkZSA8bGludXgvaW8u aD4KKworI2luY2x1ZGUgPGFzbS9jcHUuaD4KKyNpbmNsdWRlIDxhc20vc21wLmg+CisjaW5jbHVk ZSA8YXNtL2NhY2hlaW5mby5oPgorI2luY2x1ZGUgPGFzbS9zcGVjLWN0cmwuaD4KKyNpbmNsdWRl IDxhc20vZGVsYXkuaD4KKyNpZmRlZiBDT05GSUdfWDg2XzY0CisjIGluY2x1ZGUgPGFzbS9zZXRf bWVtb3J5Lmg+CisjZW5kaWYKKworI2luY2x1ZGUgImNwdS5oIgorCisvKgorICogbm9kZXNfcGVy X3NvY2tldDogU3RvcmVzIHRoZSBudW1iZXIgb2Ygbm9kZXMgcGVyIHNvY2tldC4KKyAqIFJlZmVy IHRvIENQVUlEIEZuODAwMF8wMDFFX0VDWCBOb2RlIElkZW50aWZpZXJzWzEwOjhdCisgKi8KK3N0 YXRpYyB1MzIgbm9kZXNfcGVyX3NvY2tldCA9IDE7CisKKyNpZmRlZiBDT05GSUdfTlVNQQorLyoK KyAqIFRvIHdvcmthcm91bmQgYnJva2VuIE5VTUEgY29uZmlnLiAgUmVhZCB0aGUgY29tbWVudCBp bgorICogc3JhdF9kZXRlY3Rfbm9kZSgpLgorICovCitzdGF0aWMgaW50IG5lYXJieV9ub2RlKGlu dCBhcGljaWQpCit7CisJaW50IGksIG5vZGU7CisKKwlmb3IgKGkgPSBhcGljaWQgLSAxOyBpID49 IDA7IGktLSkgeworCQlub2RlID0gX19hcGljaWRfdG9fbm9kZVtpXTsKKwkJaWYgKG5vZGUgIT0g TlVNQV9OT19OT0RFICYmIG5vZGVfb25saW5lKG5vZGUpKQorCQkJcmV0dXJuIG5vZGU7CisJfQor CWZvciAoaSA9IGFwaWNpZCArIDE7IGkgPCBNQVhfTE9DQUxfQVBJQzsgaSsrKSB7CisJCW5vZGUg PSBfX2FwaWNpZF90b19ub2RlW2ldOworCQlpZiAobm9kZSAhPSBOVU1BX05PX05PREUgJiYgbm9k ZV9vbmxpbmUobm9kZSkpCisJCQlyZXR1cm4gbm9kZTsKKwl9CisJcmV0dXJuIGZpcnN0X25vZGUo bm9kZV9vbmxpbmVfbWFwKTsgLyogU2hvdWxkbid0IGhhcHBlbiAqLworfQorI2VuZGlmCisKKy8q CisgKiBGaXh1cCBjb3JlIHRvcG9sb2d5IGluZm9ybWF0aW9uIGZvcgorICogKDEpIEh5Z29uIG11 bHRpLW5vZGUgcHJvY2Vzc29ycworICogICAgIEFzc3VtcHRpb246IE51bWJlciBvZiBjb3JlcyBp biBlYWNoIGludGVybmFsIG5vZGUgaXMgdGhlIHNhbWUuCisgKiAoMikgSHlnb24gcHJvY2Vzc29y cyBzdXBwb3J0aW5nIGNvbXB1dGUgdW5pdHMKKyAqLworc3RhdGljIHZvaWQgaHlnb25fZ2V0X3Rv cG9sb2d5KHN0cnVjdCBjcHVpbmZvX3g4NiAqYykKK3sKKwl1OCBub2RlX2lkOworCWludCBjcHUg PSBzbXBfcHJvY2Vzc29yX2lkKCk7CisKKwkvKiBnZXQgaW5mb3JtYXRpb24gcmVxdWlyZWQgZm9y IG11bHRpLW5vZGUgcHJvY2Vzc29ycyAqLworCWlmIChib290X2NwdV9oYXMoWDg2X0ZFQVRVUkVf VE9QT0VYVCkpIHsKKwkJaW50IGVycjsKKwkJdTMyIGVheCwgZWJ4LCBlY3gsIGVkeDsKKworCQlj cHVpZCgweDgwMDAwMDFlLCAmZWF4LCAmZWJ4LCAmZWN4LCAmZWR4KTsKKworCQlub2RlX2lkICA9 IGVjeCAmIDB4ZmY7CisJCXNtcF9udW1fc2libGluZ3MgPSAoKGVieCA+PiA4KSAmIDB4ZmYpICsg MTsKKworCQljLT5jcHVfY29yZV9pZCA9IGVieCAmIDB4ZmY7CisKKwkJaWYgKHNtcF9udW1fc2li bGluZ3MgPiAxKQorCQkJYy0+eDg2X21heF9jb3JlcyAvPSBzbXBfbnVtX3NpYmxpbmdzOworCisJ CS8qCisJCSAqIEluIGNhc2UgbGVhZiBCIGlzIGF2YWlsYWJsZSwgdXNlIGl0IHRvIGRlcml2ZQor CQkgKiB0b3BvbG9neSBpbmZvcm1hdGlvbi4KKwkJICovCisJCWVyciA9IGRldGVjdF9leHRlbmRl ZF90b3BvbG9neShjKTsKKwkJaWYgKCFlcnIpCisJCQljLT54ODZfY29yZWlkX2JpdHMgPSBnZXRf Y291bnRfb3JkZXIoYy0+eDg2X21heF9jb3Jlcyk7CisKKwl9IGVsc2UgaWYgKGNwdV9oYXMoYywg WDg2X0ZFQVRVUkVfTk9ERUlEX01TUikpIHsKKwkJdTY0IHZhbHVlOworCisJCXJkbXNybChNU1Jf RkFNMTBIX05PREVfSUQsIHZhbHVlKTsKKwkJbm9kZV9pZCA9IHZhbHVlICYgNzsKKworCQlwZXJf Y3B1KGNwdV9sbGNfaWQsIGNwdSkgPSBub2RlX2lkOworCX0gZWxzZQorCQlyZXR1cm47CisKKwlp ZiAobm9kZXNfcGVyX3NvY2tldCA+IDEpCisJCXNldF9jcHVfY2FwKGMsIFg4Nl9GRUFUVVJFX0FN RF9EQ00pOworfQorCisvKgorICogT24gSHlnb24gc2V0dXAgdGhlIGxvd2VyIGJpdHMgb2YgdGhl IEFQSUMgaWQgZGlzdGluZ3Vpc2ggdGhlIGNvcmVzLgorICogQXNzdW1lcyBudW1iZXIgb2YgY29y ZXMgaXMgYSBwb3dlciBvZiB0d28uCisgKi8KK3N0YXRpYyB2b2lkIGh5Z29uX2RldGVjdF9jbXAo c3RydWN0IGNwdWluZm9feDg2ICpjKQoreworCXVuc2lnbmVkIGludCBiaXRzOworCWludCBjcHUg PSBzbXBfcHJvY2Vzc29yX2lkKCk7CisKKwliaXRzID0gYy0+eDg2X2NvcmVpZF9iaXRzOworCS8q IExvdyBvcmRlciBiaXRzIGRlZmluZSB0aGUgY29yZSBpZCAoaW5kZXggb2YgY29yZSBpbiBzb2Nr ZXQpICovCisJYy0+Y3B1X2NvcmVfaWQgPSBjLT5pbml0aWFsX2FwaWNpZCAmICgoMSA8PCBiaXRz KS0xKTsKKwkvKiBDb252ZXJ0IHRoZSBpbml0aWFsIEFQSUMgSUQgaW50byB0aGUgc29ja2V0IElE ICovCisJYy0+cGh5c19wcm9jX2lkID0gYy0+aW5pdGlhbF9hcGljaWQgPj4gYml0czsKKwkvKiB1 c2Ugc29ja2V0IElEIGFsc28gZm9yIGxhc3QgbGV2ZWwgY2FjaGUgKi8KKwlwZXJfY3B1KGNwdV9s bGNfaWQsIGNwdSkgPSBjLT5waHlzX3Byb2NfaWQ7Cit9CisKK3N0YXRpYyB2b2lkIHNyYXRfZGV0 ZWN0X25vZGUoc3RydWN0IGNwdWluZm9feDg2ICpjKQoreworI2lmZGVmIENPTkZJR19OVU1BCisJ aW50IGNwdSA9IHNtcF9wcm9jZXNzb3JfaWQoKTsKKwlpbnQgbm9kZTsKKwl1bnNpZ25lZCBpbnQg YXBpY2lkID0gYy0+YXBpY2lkOworCisJbm9kZSA9IG51bWFfY3B1X25vZGUoY3B1KTsKKwlpZiAo bm9kZSA9PSBOVU1BX05PX05PREUpCisJCW5vZGUgPSBwZXJfY3B1KGNwdV9sbGNfaWQsIGNwdSk7 CisKKwkvKgorCSAqIE9uIG11bHRpLWZhYnJpYyBwbGF0Zm9ybSAoZS5nLiBOdW1hc2NhbGUgTnVt YUNoaXApIGEKKwkgKiBwbGF0Zm9ybS1zcGVjaWZpYyBoYW5kbGVyIG5lZWRzIHRvIGJlIGNhbGxl ZCB0byBmaXh1cCBzb21lCisJICogSURzIG9mIHRoZSBDUFUuCisJICovCisJaWYgKHg4Nl9jcHVp bml0LmZpeHVwX2NwdV9pZCkKKwkJeDg2X2NwdWluaXQuZml4dXBfY3B1X2lkKGMsIG5vZGUpOwor CisJaWYgKCFub2RlX29ubGluZShub2RlKSkgeworCQkvKgorCQkgKiBUd28gcG9zc2liaWxpdGll cyBoZXJlOgorCQkgKgorCQkgKiAtIFRoZSBDUFUgaXMgbWlzc2luZyBtZW1vcnkgYW5kIG5vIG5v ZGUgd2FzIGNyZWF0ZWQuICBJbgorCQkgKiAgIHRoYXQgY2FzZSB0cnkgcGlja2luZyBvbmUgZnJv bSBhIG5lYXJieSBDUFUuCisJCSAqCisJCSAqIC0gVGhlIEFQSUMgSURzIGRpZmZlciBmcm9tIHRo ZSBIeXBlclRyYW5zcG9ydCBub2RlIElEcy4KKwkJICogICBBc3N1bWUgdGhleSBhcmUgYWxsIGlu Y3JlYXNlZCBieSBhIGNvbnN0YW50IG9mZnNldCwgYnV0CisJCSAqICAgaW4gdGhlIHNhbWUgb3Jk ZXIgYXMgdGhlIEhUIG5vZGVpZHMuICBJZiB0aGF0IGRvZXNuJ3QKKwkJICogICByZXN1bHQgaW4g YSB1c2FibGUgbm9kZSBmYWxsIGJhY2sgdG8gdGhlIHBhdGggZm9yIHRoZQorCQkgKiAgIHByZXZp b3VzIGNhc2UuCisJCSAqCisJCSAqIFRoaXMgd29ya2Fyb3VuZCBvcGVyYXRlcyBkaXJlY3RseSBv biB0aGUgbWFwcGluZyBiZXR3ZWVuCisJCSAqIEFQSUMgSUQgYW5kIE5VTUEgbm9kZSwgYXNzdW1p bmcgY2VydGFpbiByZWxhdGlvbnNoaXAKKwkJICogYmV0d2VlbiBBUElDIElELCBIVCBub2RlIElE IGFuZCBOVU1BIHRvcG9sb2d5LiAgQXMgZ29pbmcKKwkJICogdGhyb3VnaCBDUFUgbWFwcGluZyBt YXkgYWx0ZXIgdGhlIG91dGNvbWUsIGRpcmVjdGx5CisJCSAqIGFjY2VzcyBfX2FwaWNpZF90b19u b2RlW10uCisJCSAqLworCQlpbnQgaHRfbm9kZWlkID0gYy0+aW5pdGlhbF9hcGljaWQ7CisKKwkJ aWYgKF9fYXBpY2lkX3RvX25vZGVbaHRfbm9kZWlkXSAhPSBOVU1BX05PX05PREUpCisJCQlub2Rl ID0gX19hcGljaWRfdG9fbm9kZVtodF9ub2RlaWRdOworCQkvKiBQaWNrIGEgbmVhcmJ5IG5vZGUg Ki8KKwkJaWYgKCFub2RlX29ubGluZShub2RlKSkKKwkJCW5vZGUgPSBuZWFyYnlfbm9kZShhcGlj aWQpOworCX0KKwludW1hX3NldF9ub2RlKGNwdSwgbm9kZSk7CisjZW5kaWYKK30KKworc3RhdGlj IHZvaWQgZWFybHlfaW5pdF9oeWdvbl9tYyhzdHJ1Y3QgY3B1aW5mb194ODYgKmMpCit7CisjaWZk ZWYgQ09ORklHX1NNUAorCXVuc2lnbmVkIGludCBiaXRzLCBlY3g7CisKKwkvKiBNdWx0aSBjb3Jl IENQVT8gKi8KKwlpZiAoYy0+ZXh0ZW5kZWRfY3B1aWRfbGV2ZWwgPCAweDgwMDAwMDA4KQorCQly ZXR1cm47CisKKwllY3ggPSBjcHVpZF9lY3goMHg4MDAwMDAwOCk7CisKKwljLT54ODZfbWF4X2Nv cmVzID0gKGVjeCAmIDB4ZmYpICsgMTsKKworCS8qIENQVSB0ZWxsaW5nIHVzIHRoZSBjb3JlIGlk IGJpdHMgc2hpZnQ/ICovCisJYml0cyA9IChlY3ggPj4gMTIpICYgMHhGOworCisJLyogT3RoZXJ3 aXNlIHJlY29tcHV0ZSAqLworCWlmIChiaXRzID09IDApIHsKKwkJd2hpbGUgKCgxIDw8IGJpdHMp IDwgYy0+eDg2X21heF9jb3JlcykKKwkJCWJpdHMrKzsKKwl9CisKKwljLT54ODZfY29yZWlkX2Jp dHMgPSBiaXRzOworI2VuZGlmCit9CisKK3N0YXRpYyB2b2lkIGJzcF9pbml0X2h5Z29uKHN0cnVj dCBjcHVpbmZvX3g4NiAqYykKK3sKKyNpZmRlZiBDT05GSUdfWDg2XzY0CisJdW5zaWduZWQgbG9u ZyBsb25nIHRzZWc7CisKKwkvKgorCSAqIFNwbGl0IHVwIGRpcmVjdCBtYXBwaW5nIGFyb3VuZCB0 aGUgVFNFRyBTTU0gYXJlYS4KKwkgKiBEb24ndCBkbyBpdCBmb3IgZ2JwYWdlcyBiZWNhdXNlIHRo ZXJlIHNlZW1zIHZlcnkgbGl0dGxlCisJICogYmVuZWZpdCBpbiBkb2luZyBzby4KKwkgKi8KKwlp ZiAoIXJkbXNybF9zYWZlKE1TUl9LOF9UU0VHX0FERFIsICZ0c2VnKSkgeworCQl1bnNpZ25lZCBs b25nIHBmbiA9IHRzZWcgPj4gUEFHRV9TSElGVDsKKworCQlwcl9kZWJ1ZygidHNlZzogJTAxMGxs eFxuIiwgdHNlZyk7CisJCWlmIChwZm5fcmFuZ2VfaXNfbWFwcGVkKHBmbiwgcGZuICsgMSkpCisJ CQlzZXRfbWVtb3J5XzRrKCh1bnNpZ25lZCBsb25nKV9fdmEodHNlZyksIDEpOworCX0KKyNlbmRp ZgorCisJaWYgKGNwdV9oYXMoYywgWDg2X0ZFQVRVUkVfQ09OU1RBTlRfVFNDKSkgeworCQl1NjQg dmFsOworCisJCXJkbXNybChNU1JfSzdfSFdDUiwgdmFsKTsKKwkJaWYgKCEodmFsICYgQklUKDI0 KSkpCisJCQlwcl93YXJuKEZXX0JVRyAiVFNDIGRvZXNuJ3QgY291bnQgd2l0aCBQMCBmcmVxdWVu Y3khXG4iKTsKKwl9CisKKwlpZiAoY3B1X2hhcyhjLCBYODZfRkVBVFVSRV9NV0FJVFgpKQorCQl1 c2VfbXdhaXR4X2RlbGF5KCk7CisKKwlpZiAoYm9vdF9jcHVfaGFzKFg4Nl9GRUFUVVJFX1RPUE9F WFQpKSB7CisJCXUzMiBlY3g7CisKKwkJZWN4ID0gY3B1aWRfZWN4KDB4ODAwMDAwMWUpOworCQlu b2Rlc19wZXJfc29ja2V0ID0gKChlY3ggPj4gOCkgJiA3KSArIDE7CisJfSBlbHNlIGlmIChib290 X2NwdV9oYXMoWDg2X0ZFQVRVUkVfTk9ERUlEX01TUikpIHsKKwkJdTY0IHZhbHVlOworCisJCXJk bXNybChNU1JfRkFNMTBIX05PREVfSUQsIHZhbHVlKTsKKwkJbm9kZXNfcGVyX3NvY2tldCA9ICgo dmFsdWUgPj4gMykgJiA3KSArIDE7CisJfQorCisJaWYgKCFib290X2NwdV9oYXMoWDg2X0ZFQVRV UkVfQU1EX1NTQkQpICYmCisJICAgICFib290X2NwdV9oYXMoWDg2X0ZFQVRVUkVfVklSVF9TU0JE KSkgeworCQkvKgorCQkgKiBUcnkgdG8gY2FjaGUgdGhlIGJhc2UgdmFsdWUgc28gZnVydGhlciBv cGVyYXRpb25zIGNhbgorCQkgKiBhdm9pZCBSTVcuIElmIHRoYXQgZmF1bHRzLCBkbyBub3QgZW5h YmxlIFNTQkQuCisJCSAqLworCQlpZiAoIXJkbXNybF9zYWZlKE1TUl9BTUQ2NF9MU19DRkcsICZ4 ODZfYW1kX2xzX2NmZ19iYXNlKSkgeworCQkJc2V0dXBfZm9yY2VfY3B1X2NhcChYODZfRkVBVFVS RV9MU19DRkdfU1NCRCk7CisJCQlzZXR1cF9mb3JjZV9jcHVfY2FwKFg4Nl9GRUFUVVJFX1NTQkQp OworCQkJeDg2X2FtZF9sc19jZmdfc3NiZF9tYXNrID0gMVVMTCA8PCAxMDsKKwkJfQorCX0KK30K Kworc3RhdGljIHZvaWQgZWFybHlfaW5pdF9oeWdvbihzdHJ1Y3QgY3B1aW5mb194ODYgKmMpCit7 CisJdTMyIGR1bW15OworCisJZWFybHlfaW5pdF9oeWdvbl9tYyhjKTsKKworCXJkbXNyX3NhZmUo TVNSX0FNRDY0X1BBVENIX0xFVkVMLCAmYy0+bWljcm9jb2RlLCAmZHVtbXkpOworCisJLyoKKwkg KiBjLT54ODZfcG93ZXIgaXMgODAwMF8wMDA3IGVkeC4gQml0IDggaXMgVFNDIHJ1bnMgYXQgY29u c3RhbnQgcmF0ZQorCSAqIHdpdGggUC9UIHN0YXRlcyBhbmQgZG9lcyBub3Qgc3RvcCBpbiBkZWVw IEMtc3RhdGVzCisJICovCisJaWYgKGMtPng4Nl9wb3dlciAmICgxIDw8IDgpKSB7CisJCXNldF9j cHVfY2FwKGMsIFg4Nl9GRUFUVVJFX0NPTlNUQU5UX1RTQyk7CisJCXNldF9jcHVfY2FwKGMsIFg4 Nl9GRUFUVVJFX05PTlNUT1BfVFNDKTsKKwl9CisKKwkvKiBCaXQgMTIgb2YgODAwMF8wMDA3IGVk eCBpcyBhY2N1bXVsYXRlZCBwb3dlciBtZWNoYW5pc20uICovCisJaWYgKGMtPng4Nl9wb3dlciAm IEJJVCgxMikpCisJCXNldF9jcHVfY2FwKGMsIFg4Nl9GRUFUVVJFX0FDQ19QT1dFUik7CisKKwlz ZXRfY3B1X2NhcChjLCBYODZfRkVBVFVSRV9TWVNDQUxMMzIpOworCisjaWYgZGVmaW5lZChDT05G SUdfWDg2X0xPQ0FMX0FQSUMpICYmIGRlZmluZWQoQ09ORklHX1BDSSkKKwkvKgorCSAqIEFwaWNJ RCBjYW4gYWx3YXlzIGJlIHRyZWF0ZWQgYXMgYW4gOC1iaXQgdmFsdWUgZm9yIEh5Z29uIEFQSUMg U28sIHdlCisJICogY2FuIHNhZmVseSBzZXQgWDg2X0ZFQVRVUkVfRVhURF9BUElDSUQgdW5jb25k aXRpb25hbGx5LgorCSAqLworCWlmIChib290X2NwdV9oYXMoWDg2X0ZFQVRVUkVfQVBJQykpCisJ CXNldF9jcHVfY2FwKGMsIFg4Nl9GRUFUVVJFX0VYVERfQVBJQ0lEKTsKKyNlbmRpZgorCisJLyoK KwkgKiBUaGlzIGlzIG9ubHkgbmVlZGVkIHRvIHRlbGwgdGhlIGtlcm5lbCB3aGV0aGVyIHRvIHVz ZSBWTUNBTEwKKwkgKiBhbmQgVk1NQ0FMTC4gIFZNTUNBTEwgaXMgbmV2ZXIgZXhlY3V0ZWQgZXhj ZXB0IHVuZGVyIHZpcnQsIHNvCisJICogd2UgY2FuIHNldCBpdCB1bmNvbmRpdGlvbmFsbHkuCisJ ICovCisJc2V0X2NwdV9jYXAoYywgWDg2X0ZFQVRVUkVfVk1NQ0FMTCk7Cit9CisKK3N0YXRpYyB2 b2lkIGluaXRfaHlnb24oc3RydWN0IGNwdWluZm9feDg2ICpjKQoreworCWVhcmx5X2luaXRfaHln b24oYyk7CisKKwkvKgorCSAqIEJpdCAzMSBpbiBub3JtYWwgQ1BVSUQgdXNlZCBmb3Igbm9uc3Rh bmRhcmQgM0ROb3cgSUQ7CisJICogM0ROb3cgaXMgSURkIGJ5IGJpdCAzMSBpbiBleHRlbmRlZCBD UFVJRCAoMSozMiszMSkgYW55d2F5CisJICovCisJY2xlYXJfY3B1X2NhcChjLCAwKjMyKzMxKTsK KworCXNldF9jcHVfY2FwKGMsIFg4Nl9GRUFUVVJFX1JFUF9HT09EKTsKKworCS8qIGdldCBhcGlj aWQgaW5zdGVhZCBvZiBpbml0aWFsIGFwaWMgaWQgZnJvbSBjcHVpZCAqLworCWMtPmFwaWNpZCA9 IGhhcmRfc21wX3Byb2Nlc3Nvcl9pZCgpOworCisJc2V0X2NwdV9jYXAoYywgWDg2X0ZFQVRVUkVf WkVOKTsKKworCWNwdV9kZXRlY3RfY2FjaGVfc2l6ZXMoYyk7CisKKwkvKiBNdWx0aSBjb3JlIENQ VT8gKi8KKwlpZiAoYy0+ZXh0ZW5kZWRfY3B1aWRfbGV2ZWwgPj0gMHg4MDAwMDAwOCkgeworCQlo eWdvbl9kZXRlY3RfY21wKGMpOworCQloeWdvbl9nZXRfdG9wb2xvZ3koYyk7CisJCXNyYXRfZGV0 ZWN0X25vZGUoYyk7CisJfQorCisJc2V0X2NwdV9jYXAoYywgWDg2X0ZFQVRVUkVfSzgpOworCisJ aWYgKGNwdV9oYXMoYywgWDg2X0ZFQVRVUkVfWE1NMikpIHsKKwkJdW5zaWduZWQgbG9uZyBsb25n IHZhbDsKKwkJaW50IHJldDsKKworCQkvKgorCQkgKiBBIHNlcmlhbGl6aW5nIExGRU5DRSBoYXMg bGVzcyBvdmVyaGVhZCB0aGFuIE1GRU5DRSwgc28KKwkJICogdXNlIGl0IGZvciBleGVjdXRpb24g c2VyaWFsaXphdGlvbi4gIE9uIGZhbWlsaWVzIHdoaWNoCisJCSAqIGRvbid0IGhhdmUgdGhhdCBN U1IsIExGRU5DRSBpcyBhbHJlYWR5IHNlcmlhbGl6aW5nLgorCQkgKiBtc3Jfc2V0X2JpdCgpIHVz ZXMgdGhlIHNhZmUgYWNjZXNzb3JzLCB0b28sIGV2ZW4gaWYgdGhlIE1TUgorCQkgKiBpcyBub3Qg cHJlc2VudC4KKwkJICovCisJCW1zcl9zZXRfYml0KE1TUl9GMTBIX0RFQ0ZHLAorCQkJICAgIE1T Ul9GMTBIX0RFQ0ZHX0xGRU5DRV9TRVJJQUxJWkVfQklUKTsKKworCQkvKgorCQkgKiBWZXJpZnkg dGhhdCB0aGUgTVNSIHdyaXRlIHdhcyBzdWNjZXNzZnVsIChjb3VsZCBiZSBydW5uaW5nCisJCSAq IHVuZGVyIGEgaHlwZXJ2aXNvcikgYW5kIG9ubHkgdGhlbiBhc3N1bWUgdGhhdCBMRkVOQ0UgaXMK KwkJICogc2VyaWFsaXppbmcuCisJCSAqLworCQlyZXQgPSByZG1zcmxfc2FmZShNU1JfRjEwSF9E RUNGRywgJnZhbCk7CisJCWlmICghcmV0ICYmICh2YWwgJiBNU1JfRjEwSF9ERUNGR19MRkVOQ0Vf U0VSSUFMSVpFKSkgeworCQkJLyogQSBzZXJpYWxpemluZyBMRkVOQ0Ugc3RvcHMgUkRUU0Mgc3Bl Y3VsYXRpb24gKi8KKwkJCXNldF9jcHVfY2FwKGMsIFg4Nl9GRUFUVVJFX0xGRU5DRV9SRFRTQyk7 CisJCX0gZWxzZSB7CisJCQkvKiBNRkVOQ0Ugc3RvcHMgUkRUU0Mgc3BlY3VsYXRpb24gKi8KKwkJ CXNldF9jcHVfY2FwKGMsIFg4Nl9GRUFUVVJFX01GRU5DRV9SRFRTQyk7CisJCX0KKwl9CisKKwkv KgorCSAqIEh5Z29uIHByb2Nlc3NvcnMgaGF2ZSBBUElDIHRpbWVyIHJ1bm5pbmcgaW4gZGVlcCBD IHN0YXRlcy4KKwkgKi8KKwlzZXRfY3B1X2NhcChjLCBYODZfRkVBVFVSRV9BUkFUKTsKKworCS8q IEh5Z29uIENQVXMgZG9uJ3QgcmVzZXQgU1MgYXR0cmlidXRlcyBvbiBTWVNSRVQsIFhlbiBkb2Vz LiAqLworCWlmICghY3B1X2hhcyhjLCBYODZfRkVBVFVSRV9YRU5QVikpCisJCXNldF9jcHVfYnVn KGMsIFg4Nl9CVUdfU1lTUkVUX1NTX0FUVFJTKTsKK30KKworc3RhdGljIHZvaWQgY3B1X2RldGVj dF90bGJfaHlnb24oc3RydWN0IGNwdWluZm9feDg2ICpjKQoreworCXUzMiBlYngsIGVheCwgZWN4 LCBlZHg7CisJdTE2IG1hc2sgPSAweGZmZjsKKworCWlmIChjLT5leHRlbmRlZF9jcHVpZF9sZXZl bCA8IDB4ODAwMDAwMDYpCisJCXJldHVybjsKKworCWNwdWlkKDB4ODAwMDAwMDYsICZlYXgsICZl YngsICZlY3gsICZlZHgpOworCisJdGxiX2xsZF80a1tFTlRSSUVTXSA9IChlYnggPj4gMTYpICYg bWFzazsKKwl0bGJfbGxpXzRrW0VOVFJJRVNdID0gZWJ4ICYgbWFzazsKKworCS8qIEhhbmRsZSBE VExCIDJNIGFuZCA0TSBzaXplcywgZmFsbCBiYWNrIHRvIEwxIGlmIEwyIGlzIGRpc2FibGVkICov CisJaWYgKCEoKGVheCA+PiAxNikgJiBtYXNrKSkKKwkJdGxiX2xsZF8ybVtFTlRSSUVTXSA9IChj cHVpZF9lYXgoMHg4MDAwMDAwNSkgPj4gMTYpICYgMHhmZjsKKwllbHNlCisJCXRsYl9sbGRfMm1b RU5UUklFU10gPSAoZWF4ID4+IDE2KSAmIG1hc2s7CisKKwkvKiBhIDRNIGVudHJ5IHVzZXMgdHdv IDJNIGVudHJpZXMgKi8KKwl0bGJfbGxkXzRtW0VOVFJJRVNdID0gdGxiX2xsZF8ybVtFTlRSSUVT XSA+PiAxOworCisJLyogSGFuZGxlIElUTEIgMk0gYW5kIDRNIHNpemVzLCBmYWxsIGJhY2sgdG8g TDEgaWYgTDIgaXMgZGlzYWJsZWQgKi8KKwlpZiAoIShlYXggJiBtYXNrKSkgeworCQljcHVpZCgw eDgwMDAwMDA1LCAmZWF4LCAmZWJ4LCAmZWN4LCAmZWR4KTsKKwkJdGxiX2xsaV8ybVtFTlRSSUVT XSA9IGVheCAmIDB4ZmY7CisJfSBlbHNlCisJCXRsYl9sbGlfMm1bRU5UUklFU10gPSBlYXggJiBt YXNrOworCisJdGxiX2xsaV80bVtFTlRSSUVTXSA9IHRsYl9sbGlfMm1bRU5UUklFU10gPj4gMTsK K30KKworc3RhdGljIGNvbnN0IHN0cnVjdCBjcHVfZGV2IGh5Z29uX2NwdV9kZXYgPSB7CisJLmNf dmVuZG9yCT0gIkh5Z29uIiwKKwkuY19pZGVudAk9IHsgIkh5Z29uR2VudWluZSIgfSwKKwkuY19l YXJseV9pbml0ICAgPSBlYXJseV9pbml0X2h5Z29uLAorCS5jX2RldGVjdF90bGIJPSBjcHVfZGV0 ZWN0X3RsYl9oeWdvbiwKKwkuY19ic3BfaW5pdAk9IGJzcF9pbml0X2h5Z29uLAorCS5jX2luaXQJ CT0gaW5pdF9oeWdvbiwKKwkuY194ODZfdmVuZG9yCT0gWDg2X1ZFTkRPUl9IWUdPTiwKK307CisK K2NwdV9kZXZfcmVnaXN0ZXIoaHlnb25fY3B1X2Rldik7Ci0tIAoyLjcuNAoKCl9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fClhlbi1kZXZlbCBtYWlsaW5nIGxp c3QKWGVuLWRldmVsQGxpc3RzLnhlbnByb2plY3Qub3JnCmh0dHBzOi8vbGlzdHMueGVucHJvamVj dC5vcmcvbWFpbG1hbi9saXN0aW5mby94ZW4tZGV2ZWw= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp21.cstnet.cn ([159.226.251.21]:52029 "EHLO cstnet.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388317AbeGWO3g (ORCPT ); Mon, 23 Jul 2018 10:29:36 -0400 From: Pu Wen Subject: [PATCH v2 01/17] x86/cpu: create Dhyana init file and register new cpu_dev to system Date: Mon, 23 Jul 2018 21:20:21 +0800 Message-ID: <1532352037-7151-2-git-send-email-puwen@hygon.cn> In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> References: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Sender: linux-arch-owner@vger.kernel.org List-ID: To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, kvm@vger.kernel.org, xen-devel@lists.xenproject.org Message-ID: <20180723132021.jSxrvXNmkg3Z-pbMbRyHOMszDCaMpKIlk31by_Y9y2E@z> Add x86 architecture support for new processor Hygon Dhyana Family 18h. Rework to create a separated file(arch/x86/kernel/cpu/hygon.c) from the AMD init one(arch/x86/kernel/cpu/amd.c) to initialize Dhyana CPU. In this way we can remove old AMD architecture support codes from Hygon code path and generate a clear initialization flow for Hygon processors, it also reduce long-term maintenance effort. Also add hygon.c Maintainer information in accordance. To identify Hygon processors, add a new vendor type X86_VENDOR_HYGON(9) for system recognition. To enable Hygon processor config, add a separated Kconfig entry(CPU_SUP_ HYGON) for Dhyana CPU in kernel config setup. Signed-off-by: Pu Wen --- MAINTAINERS | 6 + arch/x86/Kconfig.cpu | 13 ++ arch/x86/include/asm/processor.h | 3 +- arch/x86/kernel/cpu/Makefile | 1 + arch/x86/kernel/cpu/hygon.c | 401 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 423 insertions(+), 1 deletion(-) create mode 100644 arch/x86/kernel/cpu/hygon.c diff --git a/MAINTAINERS b/MAINTAINERS index 0fe4228..ade39f2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6604,6 +6604,12 @@ S: Maintained F: mm/memory-failure.c F: mm/hwpoison-inject.c +HYGON PROCESSOR SUPPORT +M: Pu Wen +L: linux-arch@vger.kernel.org +S: Supported +F: arch/x86/kernel/cpu/hygon.c + Hyper-V CORE AND DRIVERS M: "K. Y. Srinivasan" M: Haiyang Zhang diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 638411f..2e92267 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -426,6 +426,19 @@ config CPU_SUP_AMD If unsure, say N. +config CPU_SUP_HYGON + default y + bool "Support Hygon processors" if PROCESSOR_SELECT + help + This enables detection, tunings and quirks for Hygon processors + + You need this enabled if you want your kernel to run on an + Hygon CPU. Disabling this option on other types of CPUs + makes the kernel a tiny bit smaller. Disabling it on an Hygon + CPU might render the kernel unbootable. + + If unsure, say N. + config CPU_SUP_CENTAUR default y bool "Support Centaur processors" if PROCESSOR_SELECT diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index cfd29ee..b4f4fbd 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -153,7 +153,8 @@ enum cpuid_regs_idx { #define X86_VENDOR_CENTAUR 5 #define X86_VENDOR_TRANSMETA 7 #define X86_VENDOR_NSC 8 -#define X86_VENDOR_NUM 9 +#define X86_VENDOR_HYGON 9 +#define X86_VENDOR_NUM 10 #define X86_VENDOR_UNKNOWN 0xff diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 7a40196..889ce58 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_X86_FEATURE_NAMES) += capflags.o powerflags.o obj-$(CONFIG_CPU_SUP_INTEL) += intel.o intel_pconfig.o obj-$(CONFIG_CPU_SUP_AMD) += amd.o +obj-$(CONFIG_CPU_SUP_HYGON) += hygon.o obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c new file mode 100644 index 0000000..cc296e5 --- /dev/null +++ b/arch/x86/kernel/cpu/hygon.c @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Hygon Processor Support for Linux + * + * Copyright (c) Chengdu Haiguang IC Design Co., Ltd. + * + * Author: 2018 Pu Wen + * + * This file is licensed under the terms of the GNU General + * License v2.0 or later. See file COPYING for details. + */ +#include + +#include +#include +#include +#include +#include +#ifdef CONFIG_X86_64 +# include +#endif + +#include "cpu.h" + +/* + * nodes_per_socket: Stores the number of nodes per socket. + * Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8] + */ +static u32 nodes_per_socket = 1; + +#ifdef CONFIG_NUMA +/* + * To workaround broken NUMA config. Read the comment in + * srat_detect_node(). + */ +static int nearby_node(int apicid) +{ + int i, node; + + for (i = apicid - 1; i >= 0; i--) { + node = __apicid_to_node[i]; + if (node != NUMA_NO_NODE && node_online(node)) + return node; + } + for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { + node = __apicid_to_node[i]; + if (node != NUMA_NO_NODE && node_online(node)) + return node; + } + return first_node(node_online_map); /* Shouldn't happen */ +} +#endif + +/* + * Fixup core topology information for + * (1) Hygon multi-node processors + * Assumption: Number of cores in each internal node is the same. + * (2) Hygon processors supporting compute units + */ +static void hygon_get_topology(struct cpuinfo_x86 *c) +{ + u8 node_id; + int cpu = smp_processor_id(); + + /* get information required for multi-node processors */ + if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { + int err; + u32 eax, ebx, ecx, edx; + + cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); + + node_id = ecx & 0xff; + smp_num_siblings = ((ebx >> 8) & 0xff) + 1; + + c->cpu_core_id = ebx & 0xff; + + if (smp_num_siblings > 1) + c->x86_max_cores /= smp_num_siblings; + + /* + * In case leaf B is available, use it to derive + * topology information. + */ + err = detect_extended_topology(c); + if (!err) + c->x86_coreid_bits = get_count_order(c->x86_max_cores); + + } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { + u64 value; + + rdmsrl(MSR_FAM10H_NODE_ID, value); + node_id = value & 7; + + per_cpu(cpu_llc_id, cpu) = node_id; + } else + return; + + if (nodes_per_socket > 1) + set_cpu_cap(c, X86_FEATURE_AMD_DCM); +} + +/* + * On Hygon setup the lower bits of the APIC id distinguish the cores. + * Assumes number of cores is a power of two. + */ +static void hygon_detect_cmp(struct cpuinfo_x86 *c) +{ + unsigned int bits; + int cpu = smp_processor_id(); + + bits = c->x86_coreid_bits; + /* Low order bits define the core id (index of core in socket) */ + c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); + /* Convert the initial APIC ID into the socket ID */ + c->phys_proc_id = c->initial_apicid >> bits; + /* use socket ID also for last level cache */ + per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; +} + +static void srat_detect_node(struct cpuinfo_x86 *c) +{ +#ifdef CONFIG_NUMA + int cpu = smp_processor_id(); + int node; + unsigned int apicid = c->apicid; + + node = numa_cpu_node(cpu); + if (node == NUMA_NO_NODE) + node = per_cpu(cpu_llc_id, cpu); + + /* + * On multi-fabric platform (e.g. Numascale NumaChip) a + * platform-specific handler needs to be called to fixup some + * IDs of the CPU. + */ + if (x86_cpuinit.fixup_cpu_id) + x86_cpuinit.fixup_cpu_id(c, node); + + if (!node_online(node)) { + /* + * Two possibilities here: + * + * - The CPU is missing memory and no node was created. In + * that case try picking one from a nearby CPU. + * + * - The APIC IDs differ from the HyperTransport node IDs. + * Assume they are all increased by a constant offset, but + * in the same order as the HT nodeids. If that doesn't + * result in a usable node fall back to the path for the + * previous case. + * + * This workaround operates directly on the mapping between + * APIC ID and NUMA node, assuming certain relationship + * between APIC ID, HT node ID and NUMA topology. As going + * through CPU mapping may alter the outcome, directly + * access __apicid_to_node[]. + */ + int ht_nodeid = c->initial_apicid; + + if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) + node = __apicid_to_node[ht_nodeid]; + /* Pick a nearby node */ + if (!node_online(node)) + node = nearby_node(apicid); + } + numa_set_node(cpu, node); +#endif +} + +static void early_init_hygon_mc(struct cpuinfo_x86 *c) +{ +#ifdef CONFIG_SMP + unsigned int bits, ecx; + + /* Multi core CPU? */ + if (c->extended_cpuid_level < 0x80000008) + return; + + ecx = cpuid_ecx(0x80000008); + + c->x86_max_cores = (ecx & 0xff) + 1; + + /* CPU telling us the core id bits shift? */ + bits = (ecx >> 12) & 0xF; + + /* Otherwise recompute */ + if (bits == 0) { + while ((1 << bits) < c->x86_max_cores) + bits++; + } + + c->x86_coreid_bits = bits; +#endif +} + +static void bsp_init_hygon(struct cpuinfo_x86 *c) +{ +#ifdef CONFIG_X86_64 + unsigned long long tseg; + + /* + * Split up direct mapping around the TSEG SMM area. + * Don't do it for gbpages because there seems very little + * benefit in doing so. + */ + if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { + unsigned long pfn = tseg >> PAGE_SHIFT; + + pr_debug("tseg: %010llx\n", tseg); + if (pfn_range_is_mapped(pfn, pfn + 1)) + set_memory_4k((unsigned long)__va(tseg), 1); + } +#endif + + if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { + u64 val; + + rdmsrl(MSR_K7_HWCR, val); + if (!(val & BIT(24))) + pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); + } + + if (cpu_has(c, X86_FEATURE_MWAITX)) + use_mwaitx_delay(); + + if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { + u32 ecx; + + ecx = cpuid_ecx(0x8000001e); + nodes_per_socket = ((ecx >> 8) & 7) + 1; + } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { + u64 value; + + rdmsrl(MSR_FAM10H_NODE_ID, value); + nodes_per_socket = ((value >> 3) & 7) + 1; + } + + if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && + !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) { + /* + * Try to cache the base value so further operations can + * avoid RMW. If that faults, do not enable SSBD. + */ + if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { + setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); + setup_force_cpu_cap(X86_FEATURE_SSBD); + x86_amd_ls_cfg_ssbd_mask = 1ULL << 10; + } + } +} + +static void early_init_hygon(struct cpuinfo_x86 *c) +{ + u32 dummy; + + early_init_hygon_mc(c); + + rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); + + /* + * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate + * with P/T states and does not stop in deep C-states + */ + if (c->x86_power & (1 << 8)) { + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); + } + + /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ + if (c->x86_power & BIT(12)) + set_cpu_cap(c, X86_FEATURE_ACC_POWER); + + set_cpu_cap(c, X86_FEATURE_SYSCALL32); + +#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) + /* + * ApicID can always be treated as an 8-bit value for Hygon APIC So, we + * can safely set X86_FEATURE_EXTD_APICID unconditionally. + */ + if (boot_cpu_has(X86_FEATURE_APIC)) + set_cpu_cap(c, X86_FEATURE_EXTD_APICID); +#endif + + /* + * This is only needed to tell the kernel whether to use VMCALL + * and VMMCALL. VMMCALL is never executed except under virt, so + * we can set it unconditionally. + */ + set_cpu_cap(c, X86_FEATURE_VMMCALL); +} + +static void init_hygon(struct cpuinfo_x86 *c) +{ + early_init_hygon(c); + + /* + * Bit 31 in normal CPUID used for nonstandard 3DNow ID; + * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway + */ + clear_cpu_cap(c, 0*32+31); + + set_cpu_cap(c, X86_FEATURE_REP_GOOD); + + /* get apicid instead of initial apic id from cpuid */ + c->apicid = hard_smp_processor_id(); + + set_cpu_cap(c, X86_FEATURE_ZEN); + + cpu_detect_cache_sizes(c); + + /* Multi core CPU? */ + if (c->extended_cpuid_level >= 0x80000008) { + hygon_detect_cmp(c); + hygon_get_topology(c); + srat_detect_node(c); + } + + set_cpu_cap(c, X86_FEATURE_K8); + + if (cpu_has(c, X86_FEATURE_XMM2)) { + unsigned long long val; + int ret; + + /* + * A serializing LFENCE has less overhead than MFENCE, so + * use it for execution serialization. On families which + * don't have that MSR, LFENCE is already serializing. + * msr_set_bit() uses the safe accessors, too, even if the MSR + * is not present. + */ + msr_set_bit(MSR_F10H_DECFG, + MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); + + /* + * Verify that the MSR write was successful (could be running + * under a hypervisor) and only then assume that LFENCE is + * serializing. + */ + ret = rdmsrl_safe(MSR_F10H_DECFG, &val); + if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) { + /* A serializing LFENCE stops RDTSC speculation */ + set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); + } else { + /* MFENCE stops RDTSC speculation */ + set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); + } + } + + /* + * Hygon processors have APIC timer running in deep C states. + */ + set_cpu_cap(c, X86_FEATURE_ARAT); + + /* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */ + if (!cpu_has(c, X86_FEATURE_XENPV)) + set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); +} + +static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c) +{ + u32 ebx, eax, ecx, edx; + u16 mask = 0xfff; + + if (c->extended_cpuid_level < 0x80000006) + return; + + cpuid(0x80000006, &eax, &ebx, &ecx, &edx); + + tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; + tlb_lli_4k[ENTRIES] = ebx & mask; + + /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ + if (!((eax >> 16) & mask)) + tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; + else + tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; + + /* a 4M entry uses two 2M entries */ + tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; + + /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ + if (!(eax & mask)) { + cpuid(0x80000005, &eax, &ebx, &ecx, &edx); + tlb_lli_2m[ENTRIES] = eax & 0xff; + } else + tlb_lli_2m[ENTRIES] = eax & mask; + + tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; +} + +static const struct cpu_dev hygon_cpu_dev = { + .c_vendor = "Hygon", + .c_ident = { "HygonGenuine" }, + .c_early_init = early_init_hygon, + .c_detect_tlb = cpu_detect_tlb_hygon, + .c_bsp_init = bsp_init_hygon, + .c_init = init_hygon, + .c_x86_vendor = X86_VENDOR_HYGON, +}; + +cpu_dev_register(hygon_cpu_dev); -- 2.7.4