From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pu Wen Subject: [PATCH v2 02/17] x86/cache: get Dhyana cache size/leaves and setup cache cpumap Date: Mon, 23 Jul 2018 21:20:22 +0800 Message-ID: <1532352037-7151-3-git-send-email-puwen@hygon.cn> References: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-arch@vger.kernel.org, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org List-Id: linux-arch.vger.kernel.org SHlnb24gRGh5YW5hIHByb2Nlc3NvciBoYXMgdGhlIHRvcG9sb2d5IGV4dGVuc2lvbnMgYml0IGlu IENQVUlELgpXaXRoIHRoaXMgYml0IGtlcm5lbCBjYW4gZ2V0IHRoZSBjYWNoZSBpbmZvLiBTbyBh ZGQgc3VwcG9ydAppbiBjcHVpZDRfY2FjaGVfbG9va3VwX3JlZ3MoKSB0byBnZXQgdGhlIGNvcnJl Y3QgY2FjaGUgc2l6ZS4KCkRoeWFuYSBhbHNvIGZpbmQgbnVtX2NhY2hlX2xlYXZlcyB2aWEgQ1BV SUQgbGVhZiAweDgwMDAwMDFkLCBzbwphZGQgSHlnb24gc3VwcG9ydCBpbiBmaW5kX251bV9jYWNo ZV9sZWF2ZXMoKS4KCkFsc28gYWRkIGNhY2hlaW5mb19oeWdvbl9pbml0X2xsY19pZCgpIGFuZCBp bml0X2h5Z29uX2NhY2hlaW5mbygpCmZ1bmN0aW9ucyB0byBpbml0aWFsaXplIERoeWFuYSBjYWNo ZSBpbmZvLiBTZXR1cCBjYWNoZSBjcHVtYXAgaW4KdGhlIHNhbWUgd2F5IGFzIEFNRCBkb2VzLgoK U2lnbmVkLW9mZi1ieTogUHUgV2VuIDxwdXdlbkBoeWdvbi5jbj4KLS0tCiBhcmNoL3g4Ni9pbmNs dWRlL2FzbS9jYWNoZWluZm8uaCB8ICAxICsKIGFyY2gveDg2L2tlcm5lbC9jcHUvY2FjaGVpbmZv LmMgIHwgMzEgKysrKysrKysrKysrKysrKysrKysrKysrKysrKystLQogYXJjaC94ODYva2VybmVs L2NwdS9jcHUuaCAgICAgICAgfCAgMSArCiBhcmNoL3g4Ni9rZXJuZWwvY3B1L2h5Z29uLmMgICAg ICB8ICAzICsrKwogNCBmaWxlcyBjaGFuZ2VkLCAzNCBpbnNlcnRpb25zKCspLCAyIGRlbGV0aW9u cygtKQoKZGlmZiAtLWdpdCBhL2FyY2gveDg2L2luY2x1ZGUvYXNtL2NhY2hlaW5mby5oIGIvYXJj aC94ODYvaW5jbHVkZS9hc20vY2FjaGVpbmZvLmgKaW5kZXggZTk1OGUyOC4uODZiNjNjNyAxMDA2 NDQKLS0tIGEvYXJjaC94ODYvaW5jbHVkZS9hc20vY2FjaGVpbmZvLmgKKysrIGIvYXJjaC94ODYv aW5jbHVkZS9hc20vY2FjaGVpbmZvLmgKQEAgLTMsNSArMyw2IEBACiAjZGVmaW5lIF9BU01fWDg2 X0NBQ0hFSU5GT19ICiAKIHZvaWQgY2FjaGVpbmZvX2FtZF9pbml0X2xsY19pZChzdHJ1Y3QgY3B1 aW5mb194ODYgKmMsIGludCBjcHUsIHU4IG5vZGVfaWQpOwordm9pZCBjYWNoZWluZm9faHlnb25f aW5pdF9sbGNfaWQoc3RydWN0IGNwdWluZm9feDg2ICpjLCBpbnQgY3B1LCB1OCBub2RlX2lkKTsK IAogI2VuZGlmIC8qIF9BU01fWDg2X0NBQ0hFSU5GT19IICovCmRpZmYgLS1naXQgYS9hcmNoL3g4 Ni9rZXJuZWwvY3B1L2NhY2hlaW5mby5jIGIvYXJjaC94ODYva2VybmVsL2NwdS9jYWNoZWluZm8u YwppbmRleCAwYzVmY2JkLi5kYzFiOTM0IDEwMDY0NAotLS0gYS9hcmNoL3g4Ni9rZXJuZWwvY3B1 L2NhY2hlaW5mby5jCisrKyBiL2FyY2gveDg2L2tlcm5lbC9jcHUvY2FjaGVpbmZvLmMKQEAgLTYw Miw2ICs2MDIsMTAgQEAgY3B1aWQ0X2NhY2hlX2xvb2t1cF9yZWdzKGludCBpbmRleCwgc3RydWN0 IF9jcHVpZDRfaW5mb19yZWdzICp0aGlzX2xlYWYpCiAJCWVsc2UKIAkJCWFtZF9jcHVpZDQoaW5k ZXgsICZlYXgsICZlYngsICZlY3gpOwogCQlhbWRfaW5pdF9sM19jYWNoZSh0aGlzX2xlYWYsIGlu ZGV4KTsKKwl9IGVsc2UgaWYgKGJvb3RfY3B1X2RhdGEueDg2X3ZlbmRvciA9PSBYODZfVkVORE9S X0hZR09OKSB7CisJCWNwdWlkX2NvdW50KDB4ODAwMDAwMWQsIGluZGV4LCAmZWF4LmZ1bGwsCisJ CQkgICAgJmVieC5mdWxsLCAmZWN4LmZ1bGwsICZlZHgpOworCQlhbWRfaW5pdF9sM19jYWNoZSh0 aGlzX2xlYWYsIGluZGV4KTsKIAl9IGVsc2UgewogCQljcHVpZF9jb3VudCg0LCBpbmRleCwgJmVh eC5mdWxsLCAmZWJ4LmZ1bGwsICZlY3guZnVsbCwgJmVkeCk7CiAJfQpAQCAtNjI1LDcgKzYyOSw4 IEBAIHN0YXRpYyBpbnQgZmluZF9udW1fY2FjaGVfbGVhdmVzKHN0cnVjdCBjcHVpbmZvX3g4NiAq YykKIAl1bmlvbiBfY3B1aWQ0X2xlYWZfZWF4CWNhY2hlX2VheDsKIAlpbnQgCQkJaSA9IC0xOwog Ci0JaWYgKGMtPng4Nl92ZW5kb3IgPT0gWDg2X1ZFTkRPUl9BTUQpCisJaWYgKGMtPng4Nl92ZW5k b3IgPT0gWDg2X1ZFTkRPUl9BTUQgfHwKKwkgICAgYy0+eDg2X3ZlbmRvciA9PSBYODZfVkVORE9S X0hZR09OKQogCQlvcCA9IDB4ODAwMDAwMWQ7CiAJZWxzZQogCQlvcCA9IDQ7CkBAIC02NzgsNiAr NjgzLDIyIEBAIHZvaWQgY2FjaGVpbmZvX2FtZF9pbml0X2xsY19pZChzdHJ1Y3QgY3B1aW5mb194 ODYgKmMsIGludCBjcHUsIHU4IG5vZGVfaWQpCiAJfQogfQogCit2b2lkIGNhY2hlaW5mb19oeWdv bl9pbml0X2xsY19pZChzdHJ1Y3QgY3B1aW5mb194ODYgKmMsIGludCBjcHUsIHU4IG5vZGVfaWQp Cit7CisJLyoKKwkgKiBXZSBtYXkgaGF2ZSBtdWx0aXBsZSBMTENzIGlmIEwzIGNhY2hlcyBleGlz dCwgc28gY2hlY2sgaWYgd2UKKwkgKiBoYXZlIGFuIEwzIGNhY2hlIGJ5IGxvb2tpbmcgYXQgdGhl IEwzIGNhY2hlIENQVUlEIGxlYWYuCisJICovCisJaWYgKCFjcHVpZF9lZHgoMHg4MDAwMDAwNikp CisJCXJldHVybjsKKworCS8qCisJICogTExDIGlzIGF0IHRoZSBjb3JlIGNvbXBsZXggbGV2ZWwu CisJICogQ29yZSBjb21wbGV4IElEIGlzIEFwaWNJZFszXSBmb3IgdGhlc2UgcHJvY2Vzc29ycy4K KwkgKi8KKwlwZXJfY3B1KGNwdV9sbGNfaWQsIGNwdSkgPSBjLT5hcGljaWQgPj4gMzsKK30KKwog dm9pZCBpbml0X2FtZF9jYWNoZWluZm8oc3RydWN0IGNwdWluZm9feDg2ICpjKQogewogCkBAIC02 OTEsNiArNzEyLDExIEBAIHZvaWQgaW5pdF9hbWRfY2FjaGVpbmZvKHN0cnVjdCBjcHVpbmZvX3g4 NiAqYykKIAl9CiB9CiAKK3ZvaWQgaW5pdF9oeWdvbl9jYWNoZWluZm8oc3RydWN0IGNwdWluZm9f eDg2ICpjKQoreworCW51bV9jYWNoZV9sZWF2ZXMgPSBmaW5kX251bV9jYWNoZV9sZWF2ZXMoYyk7 Cit9CisKIHZvaWQgaW5pdF9pbnRlbF9jYWNoZWluZm8oc3RydWN0IGNwdWluZm9feDg2ICpjKQog ewogCS8qIENhY2hlIHNpemVzICovCkBAIC05MTMsNyArOTM5LDggQEAgc3RhdGljIHZvaWQgX19j YWNoZV9jcHVtYXBfc2V0dXAodW5zaWduZWQgaW50IGNwdSwgaW50IGluZGV4LAogCWludCBpbmRl eF9tc2IsIGk7CiAJc3RydWN0IGNwdWluZm9feDg2ICpjID0gJmNwdV9kYXRhKGNwdSk7CiAKLQlp ZiAoYy0+eDg2X3ZlbmRvciA9PSBYODZfVkVORE9SX0FNRCkgeworCWlmIChjLT54ODZfdmVuZG9y ID09IFg4Nl9WRU5ET1JfQU1EIHx8CisJICAgIGMtPng4Nl92ZW5kb3IgPT0gWDg2X1ZFTkRPUl9I WUdPTikgewogCQlpZiAoX19jYWNoZV9hbWRfY3B1bWFwX3NldHVwKGNwdSwgaW5kZXgsIGJhc2Up KQogCQkJcmV0dXJuOwogCX0KZGlmZiAtLWdpdCBhL2FyY2gveDg2L2tlcm5lbC9jcHUvY3B1Lmgg Yi9hcmNoL3g4Ni9rZXJuZWwvY3B1L2NwdS5oCmluZGV4IDM4MjE2ZjYuLmMyYmE1OTYgMTAwNjQ0 Ci0tLSBhL2FyY2gveDg2L2tlcm5lbC9jcHUvY3B1LmgKKysrIGIvYXJjaC94ODYva2VybmVsL2Nw dS9jcHUuaApAQCAtNTMsNiArNTMsNyBAQCBleHRlcm4gdTMyIGdldF9zY2F0dGVyZWRfY3B1aWRf bGVhZih1bnNpZ25lZCBpbnQgbGV2ZWwsCiAJCQkJICAgIGVudW0gY3B1aWRfcmVnc19pZHggcmVn KTsKIGV4dGVybiB2b2lkIGluaXRfaW50ZWxfY2FjaGVpbmZvKHN0cnVjdCBjcHVpbmZvX3g4NiAq Yyk7CiBleHRlcm4gdm9pZCBpbml0X2FtZF9jYWNoZWluZm8oc3RydWN0IGNwdWluZm9feDg2ICpj KTsKK2V4dGVybiB2b2lkIGluaXRfaHlnb25fY2FjaGVpbmZvKHN0cnVjdCBjcHVpbmZvX3g4NiAq Yyk7CiAKIGV4dGVybiB2b2lkIGRldGVjdF9udW1fY3B1X2NvcmVzKHN0cnVjdCBjcHVpbmZvX3g4 NiAqYyk7CiBleHRlcm4gaW50IGRldGVjdF9leHRlbmRlZF90b3BvbG9neShzdHJ1Y3QgY3B1aW5m b194ODYgKmMpOwpkaWZmIC0tZ2l0IGEvYXJjaC94ODYva2VybmVsL2NwdS9oeWdvbi5jIGIvYXJj aC94ODYva2VybmVsL2NwdS9oeWdvbi5jCmluZGV4IGNjMjk2ZTUuLjBkNzdiOTEgMTAwNjQ0Ci0t LSBhL2FyY2gveDg2L2tlcm5lbC9jcHUvaHlnb24uYworKysgYi9hcmNoL3g4Ni9rZXJuZWwvY3B1 L2h5Z29uLmMKQEAgLTg1LDYgKzg1LDcgQEAgc3RhdGljIHZvaWQgaHlnb25fZ2V0X3RvcG9sb2d5 KHN0cnVjdCBjcHVpbmZvX3g4NiAqYykKIAkJaWYgKCFlcnIpCiAJCQljLT54ODZfY29yZWlkX2Jp dHMgPSBnZXRfY291bnRfb3JkZXIoYy0+eDg2X21heF9jb3Jlcyk7CiAKKwkJY2FjaGVpbmZvX2Ft ZF9pbml0X2xsY19pZChjLCBjcHUsIG5vZGVfaWQpOwogCX0gZWxzZSBpZiAoY3B1X2hhcyhjLCBY ODZfRkVBVFVSRV9OT0RFSURfTVNSKSkgewogCQl1NjQgdmFsdWU7CiAKQEAgLTMxNSw2ICszMTYs OCBAQCBzdGF0aWMgdm9pZCBpbml0X2h5Z29uKHN0cnVjdCBjcHVpbmZvX3g4NiAqYykKIAkJc3Jh dF9kZXRlY3Rfbm9kZShjKTsKIAl9CiAKKwlpbml0X2h5Z29uX2NhY2hlaW5mbyhjKTsKKwogCXNl dF9jcHVfY2FwKGMsIFg4Nl9GRUFUVVJFX0s4KTsKIAogCWlmIChjcHVfaGFzKGMsIFg4Nl9GRUFU VVJFX1hNTTIpKSB7Ci0tIAoyLjcuNAoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fClhlbi1kZXZlbCBtYWlsaW5nIGxpc3QKWGVuLWRldmVsQGxpc3RzLnhl bnByb2plY3Qub3JnCmh0dHBzOi8vbGlzdHMueGVucHJvamVjdC5vcmcvbWFpbG1hbi9saXN0aW5m by94ZW4tZGV2ZWw= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp21.cstnet.cn ([159.226.251.21]:52041 "EHLO cstnet.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2387986AbeGWO3f (ORCPT ); Mon, 23 Jul 2018 10:29:35 -0400 From: Pu Wen Subject: [PATCH v2 02/17] x86/cache: get Dhyana cache size/leaves and setup cache cpumap Date: Mon, 23 Jul 2018 21:20:22 +0800 Message-ID: <1532352037-7151-3-git-send-email-puwen@hygon.cn> In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> References: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Sender: linux-arch-owner@vger.kernel.org List-ID: To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, kvm@vger.kernel.org, xen-devel@lists.xenproject.org Message-ID: <20180723132022.LW65uOaVn4Bzl7U8Bps91X0iI0z4BPq69GOcNcwMLsw@z> Hygon Dhyana processor has the topology extensions bit in CPUID. With this bit kernel can get the cache info. So add support in cpuid4_cache_lookup_regs() to get the correct cache size. Dhyana also find num_cache_leaves via CPUID leaf 0x8000001d, so add Hygon support in find_num_cache_leaves(). Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo() functions to initialize Dhyana cache info. Setup cache cpumap in the same way as AMD does. Signed-off-by: Pu Wen --- arch/x86/include/asm/cacheinfo.h | 1 + arch/x86/kernel/cpu/cacheinfo.c | 31 +++++++++++++++++++++++++++++-- arch/x86/kernel/cpu/cpu.h | 1 + arch/x86/kernel/cpu/hygon.c | 3 +++ 4 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cacheinfo.h b/arch/x86/include/asm/cacheinfo.h index e958e28..86b63c7 100644 --- a/arch/x86/include/asm/cacheinfo.h +++ b/arch/x86/include/asm/cacheinfo.h @@ -3,5 +3,6 @@ #define _ASM_X86_CACHEINFO_H void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id); +void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id); #endif /* _ASM_X86_CACHEINFO_H */ diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index 0c5fcbd..dc1b934 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -602,6 +602,10 @@ cpuid4_cache_lookup_regs(int index, struct _cpuid4_info_regs *this_leaf) else amd_cpuid4(index, &eax, &ebx, &ecx); amd_init_l3_cache(this_leaf, index); + } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { + cpuid_count(0x8000001d, index, &eax.full, + &ebx.full, &ecx.full, &edx); + amd_init_l3_cache(this_leaf, index); } else { cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx); } @@ -625,7 +629,8 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *c) union _cpuid4_leaf_eax cache_eax; int i = -1; - if (c->x86_vendor == X86_VENDOR_AMD) + if (c->x86_vendor == X86_VENDOR_AMD || + c->x86_vendor == X86_VENDOR_HYGON) op = 0x8000001d; else op = 4; @@ -678,6 +683,22 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id) } } +void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id) +{ + /* + * We may have multiple LLCs if L3 caches exist, so check if we + * have an L3 cache by looking at the L3 cache CPUID leaf. + */ + if (!cpuid_edx(0x80000006)) + return; + + /* + * LLC is at the core complex level. + * Core complex ID is ApicId[3] for these processors. + */ + per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; +} + void init_amd_cacheinfo(struct cpuinfo_x86 *c) { @@ -691,6 +712,11 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) } } +void init_hygon_cacheinfo(struct cpuinfo_x86 *c) +{ + num_cache_leaves = find_num_cache_leaves(c); +} + void init_intel_cacheinfo(struct cpuinfo_x86 *c) { /* Cache sizes */ @@ -913,7 +939,8 @@ static void __cache_cpumap_setup(unsigned int cpu, int index, int index_msb, i; struct cpuinfo_x86 *c = &cpu_data(cpu); - if (c->x86_vendor == X86_VENDOR_AMD) { + if (c->x86_vendor == X86_VENDOR_AMD || + c->x86_vendor == X86_VENDOR_HYGON) { if (__cache_amd_cpumap_setup(cpu, index, base)) return; } diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index 38216f6..c2ba596 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -53,6 +53,7 @@ extern u32 get_scattered_cpuid_leaf(unsigned int level, enum cpuid_regs_idx reg); extern void init_intel_cacheinfo(struct cpuinfo_x86 *c); extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); +extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c); extern void detect_num_cpu_cores(struct cpuinfo_x86 *c); extern int detect_extended_topology(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index cc296e5..0d77b91 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -85,6 +85,7 @@ static void hygon_get_topology(struct cpuinfo_x86 *c) if (!err) c->x86_coreid_bits = get_count_order(c->x86_max_cores); + cacheinfo_amd_init_llc_id(c, cpu, node_id); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; @@ -315,6 +316,8 @@ static void init_hygon(struct cpuinfo_x86 *c) srat_detect_node(c); } + init_hygon_cacheinfo(c); + set_cpu_cap(c, X86_FEATURE_K8); if (cpu_has(c, X86_FEATURE_XMM2)) { -- 2.7.4