From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pu Wen Subject: [PATCH v2 03/17] x86/mtrr: get MTRR number and support TOP_MEM2 Date: Mon, 23 Jul 2018 21:20:23 +0800 Message-ID: <1532352037-7151-4-git-send-email-puwen@hygon.cn> References: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-arch@vger.kernel.org, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org List-Id: linux-arch.vger.kernel.org SHlnb24gQ1BVIGhhdmUgYSBzcGVjaWFsIG1hZ2ljIE1TUiB3YXkgdG8gZm9yY2UgV0IgZm9yIG1l bW9yeSA+NEdCLAphbmQgYWxzbyBzdXBwb3J0IFRPUF9NRU0yLiBUaGVyZWZvcmUsIGl0IGlzIG5l Y2Vzc2FyeSB0byBhZGQgSHlnb24Kc3VwcG9ydCBpbiBhbWRfc3BlY2lhbF9kZWZhdWx0X210cnIo KS4KClRoZSBNdHJyRml4RHJhbU1vZEVuIGJpdCBvbiBIeWdvbiBwbGF0Zm9ybSBzaG91bGQgYWxz byBiZSBzZXQgdG8gMSBkdXJpbmcKQklPUyBpbml0aWFsaXphdGlvbiBvZiB0aGUgZml4ZWQgTVRS UnMsIHRoZW4gY2xlYXJlZCB0byAwIGZvciBvcGVyYXRpb24uCgpUaGUgbnVtYmVyIG9mIHZhcmlh YmxlIE1UUlJzIGZvciBIeWdvbiBpcyAyIGFzIEFNRCdzLgoKU2lnbmVkLW9mZi1ieTogUHUgV2Vu IDxwdXdlbkBoeWdvbi5jbj4KLS0tCiBhcmNoL3g4Ni9rZXJuZWwvY3B1L210cnIvY2xlYW51cC5j IHwgMyArKy0KIGFyY2gveDg2L2tlcm5lbC9jcHUvbXRyci9nZW5lcmljLmMgfCAzICsrLQogYXJj aC94ODYva2VybmVsL2NwdS9tdHJyL210cnIuYyAgICB8IDIgKy0KIDMgZmlsZXMgY2hhbmdlZCwg NSBpbnNlcnRpb25zKCspLCAzIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2FyY2gveDg2L2tl cm5lbC9jcHUvbXRyci9jbGVhbnVwLmMgYi9hcmNoL3g4Ni9rZXJuZWwvY3B1L210cnIvY2xlYW51 cC5jCmluZGV4IDc2NWFmZDUuLjM2NjhjNWQgMTAwNjQ0Ci0tLSBhL2FyY2gveDg2L2tlcm5lbC9j cHUvbXRyci9jbGVhbnVwLmMKKysrIGIvYXJjaC94ODYva2VybmVsL2NwdS9tdHJyL2NsZWFudXAu YwpAQCAtODMxLDcgKzgzMSw4IEBAIGludCBfX2luaXQgYW1kX3NwZWNpYWxfZGVmYXVsdF9tdHJy KHZvaWQpCiB7CiAJdTMyIGwsIGg7CiAKLQlpZiAoYm9vdF9jcHVfZGF0YS54ODZfdmVuZG9yICE9 IFg4Nl9WRU5ET1JfQU1EKQorCWlmIChib290X2NwdV9kYXRhLng4Nl92ZW5kb3IgIT0gWDg2X1ZF TkRPUl9BTUQgJiYKKwkgICAgYm9vdF9jcHVfZGF0YS54ODZfdmVuZG9yICE9IFg4Nl9WRU5ET1Jf SFlHT04pCiAJCXJldHVybiAwOwogCWlmIChib290X2NwdV9kYXRhLng4NiA8IDB4ZikKIAkJcmV0 dXJuIDA7CmRpZmYgLS1naXQgYS9hcmNoL3g4Ni9rZXJuZWwvY3B1L210cnIvZ2VuZXJpYy5jIGIv YXJjaC94ODYva2VybmVsL2NwdS9tdHJyL2dlbmVyaWMuYwppbmRleCBlMTJlZTg2Li43MWY4Njhm IDEwMDY0NAotLS0gYS9hcmNoL3g4Ni9rZXJuZWwvY3B1L210cnIvZ2VuZXJpYy5jCisrKyBiL2Fy Y2gveDg2L2tlcm5lbC9jcHUvbXRyci9nZW5lcmljLmMKQEAgLTQ5LDcgKzQ5LDggQEAgc3RhdGlj IGlubGluZSB2b2lkIGs4X2NoZWNrX3N5c2NmZ19kcmFtX21vZF9lbih2b2lkKQogewogCXUzMiBs bywgaGk7CiAKLQlpZiAoISgoYm9vdF9jcHVfZGF0YS54ODZfdmVuZG9yID09IFg4Nl9WRU5ET1Jf QU1EKSAmJgorCWlmICghKChib290X2NwdV9kYXRhLng4Nl92ZW5kb3IgPT0gWDg2X1ZFTkRPUl9B TUQgfHwKKwkgICAgICAgYm9vdF9jcHVfZGF0YS54ODZfdmVuZG9yID09IFg4Nl9WRU5ET1JfSFlH T04pICYmCiAJICAgICAgKGJvb3RfY3B1X2RhdGEueDg2ID49IDB4MGYpKSkKIAkJcmV0dXJuOwog CmRpZmYgLS1naXQgYS9hcmNoL3g4Ni9rZXJuZWwvY3B1L210cnIvbXRyci5jIGIvYXJjaC94ODYv a2VybmVsL2NwdS9tdHJyL210cnIuYwppbmRleCA5YTE5YzgwLi41MDcwMzljIDEwMDY0NAotLS0g YS9hcmNoL3g4Ni9rZXJuZWwvY3B1L210cnIvbXRyci5jCisrKyBiL2FyY2gveDg2L2tlcm5lbC9j cHUvbXRyci9tdHJyLmMKQEAgLTEyNyw3ICsxMjcsNyBAQCBzdGF0aWMgdm9pZCBfX2luaXQgc2V0 X251bV92YXJfcmFuZ2VzKHZvaWQpCiAKIAlpZiAodXNlX2ludGVsKCkpCiAJCXJkbXNyKE1TUl9N VFJSY2FwLCBjb25maWcsIGR1bW15KTsKLQllbHNlIGlmIChpc19jcHUoQU1EKSkKKwllbHNlIGlm IChpc19jcHUoQU1EKSB8fCBpc19jcHUoSFlHT04pKQogCQljb25maWcgPSAyOwogCWVsc2UgaWYg KGlzX2NwdShDWVJJWCkgfHwgaXNfY3B1KENFTlRBVVIpKQogCQljb25maWcgPSA4OwotLSAKMi43 LjQKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpYZW4t ZGV2ZWwgbWFpbGluZyBsaXN0Clhlbi1kZXZlbEBsaXN0cy54ZW5wcm9qZWN0Lm9yZwpodHRwczov L2xpc3RzLnhlbnByb2plY3Qub3JnL21haWxtYW4vbGlzdGluZm8veGVuLWRldmVs From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp21.cstnet.cn ([159.226.251.21]:52043 "EHLO cstnet.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388064AbeGWO3e (ORCPT ); Mon, 23 Jul 2018 10:29:34 -0400 From: Pu Wen Subject: [PATCH v2 03/17] x86/mtrr: get MTRR number and support TOP_MEM2 Date: Mon, 23 Jul 2018 21:20:23 +0800 Message-ID: <1532352037-7151-4-git-send-email-puwen@hygon.cn> In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> References: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Sender: linux-arch-owner@vger.kernel.org List-ID: To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, kvm@vger.kernel.org, xen-devel@lists.xenproject.org Message-ID: <20180723132023.uCmDqZy9FoCrIlrfj4gS8gbUX8nhtY2U5dmSb3oGNdg@z> Hygon CPU have a special magic MSR way to force WB for memory >4GB, and also support TOP_MEM2. Therefore, it is necessary to add Hygon support in amd_special_default_mtrr(). The MtrrFixDramModEn bit on Hygon platform should also be set to 1 during BIOS initialization of the fixed MTRRs, then cleared to 0 for operation. The number of variable MTRRs for Hygon is 2 as AMD's. Signed-off-by: Pu Wen --- arch/x86/kernel/cpu/mtrr/cleanup.c | 3 ++- arch/x86/kernel/cpu/mtrr/generic.c | 3 ++- arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c index 765afd5..3668c5d 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -831,7 +831,8 @@ int __init amd_special_default_mtrr(void) { u32 l, h; - if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && + boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) return 0; if (boot_cpu_data.x86 < 0xf) return 0; diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index e12ee86..71f868f 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -49,7 +49,8 @@ static inline void k8_check_syscfg_dram_mod_en(void) { u32 lo, hi; - if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && + if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD || + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x0f))) return; diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 9a19c80..507039c 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -127,7 +127,7 @@ static void __init set_num_var_ranges(void) if (use_intel()) rdmsr(MSR_MTRRcap, config, dummy); - else if (is_cpu(AMD)) + else if (is_cpu(AMD) || is_cpu(HYGON)) config = 2; else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) config = 8; -- 2.7.4