From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pu Wen Subject: [PATCH v2 05/17] x86/perfctr: return perf counter and event selection bit offset Date: Mon, 23 Jul 2018 21:20:25 +0800 Message-ID: <1532352037-7151-6-git-send-email-puwen@hygon.cn> References: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-arch@vger.kernel.org, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org List-Id: linux-arch.vger.kernel.org SHlnb24gRGh5YW5hIHNoYXJlcyBzaW1pbGFyIHBlcmZjdHIgYXJjaCB3aXRoIEFNRCBmYW1pbHkg MTdoLgpJdCByZXR1cm5zIHRoZSBiaXQgb2Zmc2V0IG9mIHRoZSBwZXJmb3JtYW5jZSBjb3VudGVy IHJlZ2lzdGVyIGFuZCB0aGUKZXZlbnQgc2VsZWN0aW9uIHJlZ2lzdGVyIGZvciBIeWdvbiBDUFUg aW4gdGhlIHNpbWlsYXIgd2F5IGFzIEFNRCBkb2VzLgoKU2lnbmVkLW9mZi1ieTogUHUgV2VuIDxw dXdlbkBoeWdvbi5jbj4KLS0tCiBhcmNoL3g4Ni9rZXJuZWwvY3B1L3BlcmZjdHItd2F0Y2hkb2cu YyB8IDggKysrKysrKysKIDEgZmlsZSBjaGFuZ2VkLCA4IGluc2VydGlvbnMoKykKCmRpZmYgLS1n aXQgYS9hcmNoL3g4Ni9rZXJuZWwvY3B1L3BlcmZjdHItd2F0Y2hkb2cuYyBiL2FyY2gveDg2L2tl cm5lbC9jcHUvcGVyZmN0ci13YXRjaGRvZy5jCmluZGV4IGQzODkwODMuLmRmNDY3MDggMTAwNjQ0 Ci0tLSBhL2FyY2gveDg2L2tlcm5lbC9jcHUvcGVyZmN0ci13YXRjaGRvZy5jCisrKyBiL2FyY2gv eDg2L2tlcm5lbC9jcHUvcGVyZmN0ci13YXRjaGRvZy5jCkBAIC01MCw2ICs1MCwxMCBAQCBzdGF0 aWMgaW5saW5lIHVuc2lnbmVkIGludCBubWlfcGVyZmN0cl9tc3JfdG9fYml0KHVuc2lnbmVkIGlu dCBtc3IpCiAJCWlmIChtc3IgPj0gTVNSX0YxNUhfUEVSRl9DVFIpCiAJCQlyZXR1cm4gKG1zciAt IE1TUl9GMTVIX1BFUkZfQ1RSKSA+PiAxOwogCQlyZXR1cm4gbXNyIC0gTVNSX0s3X1BFUkZDVFIw OworCWNhc2UgWDg2X1ZFTkRPUl9IWUdPTjoKKwkJaWYgKG1zciA+PSBNU1JfRjE1SF9QRVJGX0NU UikKKwkJCXJldHVybiAobXNyIC0gTVNSX0YxNUhfUEVSRl9DVFIpID4+IDE7CisJCXJldHVybiBt c3IgLSBNU1JfSzdfUEVSRkNUUjA7CiAJY2FzZSBYODZfVkVORE9SX0lOVEVMOgogCQlpZiAoY3B1 X2hhcygmYm9vdF9jcHVfZGF0YSwgWDg2X0ZFQVRVUkVfQVJDSF9QRVJGTU9OKSkKIAkJCXJldHVy biBtc3IgLSBNU1JfQVJDSF9QRVJGTU9OX1BFUkZDVFIwOwpAQCAtNzgsNiArODIsMTAgQEAgc3Rh dGljIGlubGluZSB1bnNpZ25lZCBpbnQgbm1pX2V2bnRzZWxfbXNyX3RvX2JpdCh1bnNpZ25lZCBp bnQgbXNyKQogCQlpZiAobXNyID49IE1TUl9GMTVIX1BFUkZfQ1RMKQogCQkJcmV0dXJuIChtc3Ig LSBNU1JfRjE1SF9QRVJGX0NUTCkgPj4gMTsKIAkJcmV0dXJuIG1zciAtIE1TUl9LN19FVk5UU0VM MDsKKwljYXNlIFg4Nl9WRU5ET1JfSFlHT046CisJCWlmIChtc3IgPj0gTVNSX0YxNUhfUEVSRl9D VEwpCisJCQlyZXR1cm4gKG1zciAtIE1TUl9GMTVIX1BFUkZfQ1RMKSA+PiAxOworCQlyZXR1cm4g bXNyIC0gTVNSX0s3X0VWTlRTRUwwOwogCWNhc2UgWDg2X1ZFTkRPUl9JTlRFTDoKIAkJaWYgKGNw dV9oYXMoJmJvb3RfY3B1X2RhdGEsIFg4Nl9GRUFUVVJFX0FSQ0hfUEVSRk1PTikpCiAJCQlyZXR1 cm4gbXNyIC0gTVNSX0FSQ0hfUEVSRk1PTl9FVkVOVFNFTDA7Ci0tIAoyLjcuNAoKCl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fClhlbi1kZXZlbCBtYWlsaW5n IGxpc3QKWGVuLWRldmVsQGxpc3RzLnhlbnByb2plY3Qub3JnCmh0dHBzOi8vbGlzdHMueGVucHJv amVjdC5vcmcvbWFpbG1hbi9saXN0aW5mby94ZW4tZGV2ZWw= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp21.cstnet.cn ([159.226.251.21]:52042 "EHLO cstnet.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388097AbeGWO3e (ORCPT ); Mon, 23 Jul 2018 10:29:34 -0400 From: Pu Wen Subject: [PATCH v2 05/17] x86/perfctr: return perf counter and event selection bit offset Date: Mon, 23 Jul 2018 21:20:25 +0800 Message-ID: <1532352037-7151-6-git-send-email-puwen@hygon.cn> In-Reply-To: <1532352037-7151-1-git-send-email-puwen@hygon.cn> References: <1532352037-7151-1-git-send-email-puwen@hygon.cn> Sender: linux-arch-owner@vger.kernel.org List-ID: To: tglx@linutronix.de, bp@alien8.de, thomas.lendacky@amd.com, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, tony.luck@intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, boris.ostrovsky@oracle.com, jgross@suse.com, rjw@rjwysocki.net, lenb@kernel.org, viresh.kumar@linaro.org, mchehab@kernel.org, trenn@suse.com, shuah@kernel.org, JBeulich@suse.com, x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, kvm@vger.kernel.org, xen-devel@lists.xenproject.org Message-ID: <20180723132025.apduTrKw4cKA_wjWrwaTL4nGdXPA8A2hRHNY2Q8g968@z> Hygon Dhyana shares similar perfctr arch with AMD family 17h. It returns the bit offset of the performance counter register and the event selection register for Hygon CPU in the similar way as AMD does. Signed-off-by: Pu Wen --- arch/x86/kernel/cpu/perfctr-watchdog.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c index d389083..df46708 100644 --- a/arch/x86/kernel/cpu/perfctr-watchdog.c +++ b/arch/x86/kernel/cpu/perfctr-watchdog.c @@ -50,6 +50,10 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) if (msr >= MSR_F15H_PERF_CTR) return (msr - MSR_F15H_PERF_CTR) >> 1; return msr - MSR_K7_PERFCTR0; + case X86_VENDOR_HYGON: + if (msr >= MSR_F15H_PERF_CTR) + return (msr - MSR_F15H_PERF_CTR) >> 1; + return msr - MSR_K7_PERFCTR0; case X86_VENDOR_INTEL: if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) return msr - MSR_ARCH_PERFMON_PERFCTR0; @@ -78,6 +82,10 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr) if (msr >= MSR_F15H_PERF_CTL) return (msr - MSR_F15H_PERF_CTL) >> 1; return msr - MSR_K7_EVNTSEL0; + case X86_VENDOR_HYGON: + if (msr >= MSR_F15H_PERF_CTL) + return (msr - MSR_F15H_PERF_CTL) >> 1; + return msr - MSR_K7_EVNTSEL0; case X86_VENDOR_INTEL: if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) return msr - MSR_ARCH_PERFMON_EVENTSEL0; -- 2.7.4