From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu-cheng Yu Subject: Re: [RFC PATCH v3 19/24] x86/cet/shstk: Introduce WRUSS instruction Date: Thu, 30 Aug 2018 09:22:26 -0700 Message-ID: <1535646146.26689.11.camel@intel.com> References: <20180830143904.3168-1-yu-cheng.yu@intel.com> <20180830143904.3168-20-yu-cheng.yu@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Andy Lutomirski , Jann Horn Cc: the arch/x86 maintainers , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , kernel list , linux-doc@vger.kernel.org, Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H. J. Lu" , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek List-Id: linux-arch.vger.kernel.org On Thu, 2018-08-30 at 08:55 -0700, Andy Lutomirski wrote: > On Thu, Aug 30, 2018 at 8:39 AM, Jann Horn wrote: > > > > On Thu, Aug 30, 2018 at 4:44 PM Yu-cheng Yu > > wrote: > > > > > > > > > WRUSS is a new kernel-mode instruction but writes directly > > > to user shadow stack memory.  This is used to construct > > > a return address on the shadow stack for the signal > > > handler. > > > > > > This instruction can fault if the user shadow stack is > > > invalid shadow stack memory.  In that case, the kernel does > > > fixup. > > > > > > Signed-off-by: Yu-cheng Yu > > [...] > > > > > > +static inline int write_user_shstk_64(unsigned long addr, > > > unsigned long val) > > > +{ > > > +       int err = 0; > > > + > > > +       asm volatile("1: wrussq %1, (%0)\n" > > > +                    "2:\n" > > > +                    _ASM_EXTABLE_HANDLE(1b, 2b, > > > ex_handler_wruss) > > > +                    : > > > +                    : "r" (addr), "r" (val)); > > > + > > > +       return err; > > > +} > > What's up with "err"? You set it to zero, and then you return it, > > but > > nothing can ever set it to non-zero, right? > > > > > > > > +__visible bool ex_handler_wruss(const struct > > > exception_table_entry *fixup, > > > +                               struct pt_regs *regs, int > > > trapnr) > > > +{ > > > +       regs->ip = ex_fixup_addr(fixup); > > > +       regs->ax = -1; > > > +       return true; > > > +} > > And here you just write into regs->ax, but your "asm volatile" > > doesn't > > reserve that register. This looks wrong to me. > > > > I think you probably want to add something like an explicit > > `"+&a"(err)` output to the asm statements. > We require asm goto support these days.  How about using that?  You > won't even need a special exception handler. > > Also, please change the BUG to WARN in the you-did-it-wrong 32-bit > case.  And return -EFAULT. > > --Andy I will look into that. Yu-cheng From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com ([192.55.52.115]:63383 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727117AbeH3U3h (ORCPT ); Thu, 30 Aug 2018 16:29:37 -0400 Message-ID: <1535646146.26689.11.camel@intel.com> Subject: Re: [RFC PATCH v3 19/24] x86/cet/shstk: Introduce WRUSS instruction From: Yu-cheng Yu Date: Thu, 30 Aug 2018 09:22:26 -0700 In-Reply-To: References: <20180830143904.3168-1-yu-cheng.yu@intel.com> <20180830143904.3168-20-yu-cheng.yu@intel.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-arch-owner@vger.kernel.org List-ID: To: Andy Lutomirski , Jann Horn Cc: the arch/x86 maintainers , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , kernel list , linux-doc@vger.kernel.org, Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H. J. Lu" , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , "Ravi V. Shankar" , "Shanbhogue, Vedvyas" Message-ID: <20180830162226.tuAcrM93lY5hPtbOsNbzQcGPLVofoRBU2g5OFcNWqJg@z> On Thu, 2018-08-30 at 08:55 -0700, Andy Lutomirski wrote: > On Thu, Aug 30, 2018 at 8:39 AM, Jann Horn wrote: > > > > On Thu, Aug 30, 2018 at 4:44 PM Yu-cheng Yu > > wrote: > > > > > > > > > WRUSS is a new kernel-mode instruction but writes directly > > > to user shadow stack memory.  This is used to construct > > > a return address on the shadow stack for the signal > > > handler. > > > > > > This instruction can fault if the user shadow stack is > > > invalid shadow stack memory.  In that case, the kernel does > > > fixup. > > > > > > Signed-off-by: Yu-cheng Yu > > [...] > > > > > > +static inline int write_user_shstk_64(unsigned long addr, > > > unsigned long val) > > > +{ > > > +       int err = 0; > > > + > > > +       asm volatile("1: wrussq %1, (%0)\n" > > > +                    "2:\n" > > > +                    _ASM_EXTABLE_HANDLE(1b, 2b, > > > ex_handler_wruss) > > > +                    : > > > +                    : "r" (addr), "r" (val)); > > > + > > > +       return err; > > > +} > > What's up with "err"? You set it to zero, and then you return it, > > but > > nothing can ever set it to non-zero, right? > > > > > > > > +__visible bool ex_handler_wruss(const struct > > > exception_table_entry *fixup, > > > +                               struct pt_regs *regs, int > > > trapnr) > > > +{ > > > +       regs->ip = ex_fixup_addr(fixup); > > > +       regs->ax = -1; > > > +       return true; > > > +} > > And here you just write into regs->ax, but your "asm volatile" > > doesn't > > reserve that register. This looks wrong to me. > > > > I think you probably want to add something like an explicit > > `"+&a"(err)` output to the asm statements. > We require asm goto support these days.  How about using that?  You > won't even need a special exception handler. > > Also, please change the BUG to WARN in the you-did-it-wrong 32-bit > case.  And return -EFAULT. > > --Andy I will look into that. Yu-cheng