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Thu, 25 Jan 2024 08:38:09 -0800 (PST) Received: from [192.168.2.107] ([79.115.63.202]) by smtp.gmail.com with ESMTPSA id l9-20020a056000022900b00337d980a68asm16818099wrz.106.2024.01.25.08.38.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jan 2024 08:38:09 -0800 (PST) Message-ID: <1c58deef-bc0f-4889-bf40-54168ce9ff7c@linaro.org> Date: Thu, 25 Jan 2024 16:38:07 +0000 Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 05/28] spi: dt-bindings: samsung: add samsung,spi-fifosize property Content-Language: en-US To: Mark Brown Cc: andi.shyti@kernel.org, arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com References: <20240125145007.748295-1-tudor.ambarus@linaro.org> <20240125145007.748295-6-tudor.ambarus@linaro.org> <7ef86704-3e40-4d39-a69d-a30719c96660@sirena.org.uk> From: Tudor Ambarus In-Reply-To: <7ef86704-3e40-4d39-a69d-a30719c96660@sirena.org.uk> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/25/24 16:16, Mark Brown wrote: > On Thu, Jan 25, 2024 at 02:49:43PM +0000, Tudor Ambarus wrote: >> Up to now the SPI alias was used as an index into an array defined in >> the SPI driver to determine the SPI FIFO size. Drop the dependency on >> the SPI alias and allow the SPI nodes to specify their SPI FIFO size. > > ... > >> + samsung,spi-fifosize: >> + description: The fifo size supported by the SPI instance. >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [64, 256] > > Do we have any cases where we'd ever want to vary this independently of > the SoC - this isn't a configurable IP shipped to random integrators? The IP supports FIFO depths from 8 to 256 bytes (in powers of 2 I guess). The integrator is the one dictating the IP configuration. In gs101's case all USIxx_USI (which includes SPI, I2C, and UART) are configured with 64 bytes FIFO depths.