Re: Potential problem with the page_mapping macro and flush_dcache_page()

["David S. Miller" <davem@davemloft.net>]

From: James Bottomley <James.Bottomley@SteelEye.com>
Date: Sun, 19 Mar 2006 15:04:46 -0600

> On Sun, 2006-03-19 at 13:00 -0800, David S. Miller wrote:
> > You have physically indexed caches, thus cache coherency transactions
> > should purge all cache lines with that same physical TAG.
> 
> No, we have virtually indexed but physically tagged caches; this is why
> we have the problem (we have to select one of the aliases to flush).

This is exactly what Sparc64's caches are too, L1 D-cache is virtually
indexed and physically tagged.  But any bus coherency transaction will
update all lines with matching physical tags, otherwise things just
won't work.

> > Direct I/O is another problematic case.
> 
> OK, I confess to not ever having looked at that ... does it use
> get_user_pages() as well?

I believe so, Andrew knows...