From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ns1.suse.de ([195.135.220.2]:18078 "EHLO mx1.suse.de") by vger.kernel.org with ESMTP id S965156AbWH2RZE (ORCPT ); Tue, 29 Aug 2006 13:25:04 -0400 From: Andi Kleen Subject: Re: Why Semaphore Hardware-Dependent? Date: Tue, 29 Aug 2006 19:22:04 +0200 References: <44F395DE.10804@yahoo.com.au> <11861.1156845927@warthog.cambridge.redhat.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200608291922.04354.ak@suse.de> Sender: linux-arch-owner@vger.kernel.org To: Christoph Lameter Cc: David Howells , Nick Piggin , Arjan van de Ven , Dong Feng , Paul Mackerras , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org List-ID: On Tuesday 29 August 2006 17:56, Christoph Lameter wrote: > On Tue, 29 Aug 2006, David Howells wrote: > > > Because i386 (and x86_64) can do better by using XADDL/XADDQ. > > And Ia64 would like to use fetchadd.... This might be a dumb question, but I would expect even on altix with lots of parallel faulting threads rwsem performance be basically limited by aquiring the cache line and releasing it later to another CPU. Do you really think it will make much difference what particular atomic operation is used? The basic cost of sending the cache line over the interconnect should be all the same, no? And once the cache line is local it should be reasonably fast either way. > > CMPXCHG is not available on all archs, and may not be implemented on all archs > > through other atomic instructions. > > Which arches do not support cmpxchg? parisc at least iirc (it practically doesn't support very much atomically) and likely sparcv8. -Andi