From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.suse.de ([195.135.220.2]:50639 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757933AbXH1ISK (ORCPT ); Tue, 28 Aug 2007 04:18:10 -0400 From: Nick Piggin Date: Tue, 28 Aug 2007 18:16:02 +1000 Message-Id: <20070828081602.13582.53055.sendpatchset@linux.local0.net> In-Reply-To: <20070828081453.13582.258.sendpatchset@linux.local0.net> References: <20070828081453.13582.258.sendpatchset@linux.local0.net> Subject: [patch 7/8] powerpc: lock bitops Sender: linux-arch-owner@vger.kernel.org To: Andrew Morton Cc: Nick Piggin , Linux Arch List-ID: Add non-trivial lock bitops implementation for powerpc. Signed-off-by: Nick Piggin Acked-by: Benjamin Herrenschmidt --- include/asm-powerpc/bitops.h | 46 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) Index: linux-2.6/include/asm-powerpc/bitops.h =================================================================== --- linux-2.6.orig/include/asm-powerpc/bitops.h +++ linux-2.6/include/asm-powerpc/bitops.h @@ -86,6 +86,24 @@ static __inline__ void clear_bit(int nr, : "cc" ); } +static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr) +{ + unsigned long old; + unsigned long mask = BITOP_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); + + __asm__ __volatile__( + LWSYNC_ON_SMP +"1:" PPC_LLARX "%0,0,%3 # clear_bit_unlock\n" + "andc %0,%0,%2\n" + PPC405_ERR77(0,%3) + PPC_STLCX "%0,0,%3\n" + "bne- 1b" + : "=&r" (old), "+m" (*p) + : "r" (mask), "r" (p) + : "cc", "memory"); +} + static __inline__ void change_bit(int nr, volatile unsigned long *addr) { unsigned long old; @@ -125,6 +143,27 @@ static __inline__ int test_and_set_bit(u return (old & mask) != 0; } +static __inline__ int test_and_set_bit_lock(unsigned long nr, + volatile unsigned long *addr) +{ + unsigned long old, t; + unsigned long mask = BITOP_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); + + __asm__ __volatile__( +"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit_lock\n" + "or %1,%0,%2 \n" + PPC405_ERR77(0,%3) + PPC_STLCX "%1,0,%3 \n" + "bne- 1b" + ISYNC_ON_SMP + : "=&r" (old), "=&r" (t) + : "r" (mask), "r" (p) + : "cc", "memory"); + + return (old & mask) != 0; +} + static __inline__ int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) { @@ -185,6 +224,12 @@ static __inline__ void set_bits(unsigned #include +static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr) +{ + __asm__ __volatile__(LWSYNC_ON_SMP ::: "memory"); + __clear_bit(nr, addr); +} + /* * Return the zero-based bit position (LE, not IBM bit numbering) of * the most significant 1-bit in a double word. @@ -266,7 +311,6 @@ static __inline__ int fls(unsigned int x #include #include -#include #define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0) unsigned long find_next_zero_bit(const unsigned long *addr,