From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matthew Wilcox Subject: Re: MMIO and gcc re-ordering issue Date: Tue, 3 Jun 2008 15:35:01 -0600 Message-ID: <20080603213501.GD3549@parisc-linux.org> References: <1211852026.3286.36.camel@pasglop> <20080602072403.GA20222@flint.arm.linux.org.uk> <200806031416.18195.nickpiggin@yahoo.com.au> <20080603185541.GB3549@parisc-linux.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from palinux.external.hp.com ([192.25.206.14]:58311 "EHLO mail.parisc-linux.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752987AbYFCVfD (ORCPT ); Tue, 3 Jun 2008 17:35:03 -0400 Content-Disposition: inline In-Reply-To: Sender: linux-arch-owner@vger.kernel.org List-ID: To: Trent Piepho Cc: Linus Torvalds , Nick Piggin , Russell King , Benjamin Herrenschmidt , David Miller , linux-arch@vger.kernel.org, scottwood@freescale.com, linuxppc-dev@ozlabs.org, alan@lxorguk.ukuu.org.uk, linux-kernel@vger.kernel.org On Tue, Jun 03, 2008 at 12:57:56PM -0700, Trent Piepho wrote: > On Tue, 3 Jun 2008, Matthew Wilcox wrote: > >On Tue, Jun 03, 2008 at 11:47:00AM -0700, Trent Piepho wrote: > >>On Tue, 3 Jun 2008, Linus Torvalds wrote: > >>>On Tue, 3 Jun 2008, Nick Piggin wrote: > >>>> > >>>>Linus: on x86, memory operations to wc and wc+ memory are not ordered > >>>>with one another, or operations to other memory types (ie. load/load > >>>>and store/store reordering is allowed). Also, as you know, store/load > >>>>reordering is explicitly allowed as well, which covers all memory > >>>>types. So perhaps it is not quite true to say readl/writel is strongly > >>>>ordered by default even on x86. You would have to put in some > >>>>mfence instructions in them to make it so. > >> > >>So on x86, these could be re-ordered? > >> > >>writel(START_OPERATION, CONTROL_REGISTER); > >>status = readl(STATUS_REGISTER); > > > >You wouldn't ask for write-combining memory mapping for control or > >status registers. > > But Nick said, "store/load reordering is explicitly allowed as well, which > covers *all* memory types." Then Nick is confused. PCI only defines one way to flush posted writes to a device -- doing a read from it. There's no way that reads can be allowed to pass writes (unless you've asked for it, like with write combining). -- Intel are signing my paycheques ... these opinions are still mine "Bill, look, we understand that you're interested in selling us this operating system, but compare it to ours. We can't possibly take such a retrograde step."