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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Yinghai Lu <yinghai@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Tony Luck <tony.luck@intel.com>,
	Dominik Brodowski <linux@dominikbrodowski.net>,
	Andrew Morton <akpm@linux-foundation.org>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Greg Kroah-Hartman <gregkh@suse.de>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arch@vger.kernel.org
Subject: Re: [PATCH 01/24] PCI: Add iobusn_resource
Date: Fri, 10 Feb 2012 12:51:50 -0800	[thread overview]
Message-ID: <20120210125150.3353237c@jbarnes-desktop> (raw)
In-Reply-To: <CAE9FiQXeRGXE2RCe5S1iOE=QY37wauM=WUevjXWkMqMOjV3t7A@mail.gmail.com>

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On Mon, 6 Feb 2012 10:55:14 -0800
Yinghai Lu <yinghai@kernel.org> wrote:

> On Mon, Feb 6, 2012 at 10:48 AM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> >> +struct resource iobusn_resource = {
> >> +       .name   = "PCI busn",
> >> +       .start  = 0,
> >> +       .end    = 0xffffff,
> >> +       .flags  = IORESOURCE_BUS,
> >> +};
> >
> > I'm not sure this should be global.  iomem_resource and
> > ioport_resource *are* really global, because they refer to processor
> > address space that is the same for everybody.  But PCI bus numbers are
> > specific to PCI.  Some machines don't have PCI at all, and there are
> > different bus architectures to which this doesn't apply.
> 
> that does not hurt them.

Yes but it's superfluous and confusing if you're porting to a new arch
or looking at changes in generic code that may affect you.

> > The 0-0xffffff range is misleading because it includes both the domain
> > and the bus number, and it's meaningless to allocate ranges that cross
> > domain boundaries.  For example, [bus 0x0000f0-0x000120] includes bus
> > numbers from domain 0000 and domain 0001, which doesn't make any sense
> > because a bus can only be in one domain.
> 
> allocation code will make sure it will be cross the boundary for domain.

But that means everyone reading it will do a double take, have to dig
into the implementation, and only then say "ah yeah ok it looks
correct" rather than it being obvious from the fact that the resource
is tracked on a per-domain basis.

> > I think it would make more sense to keep this bus number resource in a
> > per-host bridge structure.  Then we wouldn't need to include the
> > domain number at all because the host bridge determines the domain.
> 
> not sure. insert the all busn_res of all peer root buses into one
> global iobusn_resource
> looks more simple.

In what sense?  Simpler in the sense of your current implementation,
but not simpler at all to someone just reading the code...

-- 
Jesse Barnes, Intel Open Source Technology Center

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  parent reply	other threads:[~2012-02-10 20:51 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-02-05  6:57 [PATCH -v5 0/24] PCI: allocate pci bus num range for unassigned bridge busn + pci rescan cleanup Yinghai Lu
2012-02-05  6:57 ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 01/24] PCI: Add iobusn_resource Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-06 18:48   ` Bjorn Helgaas
2012-02-06 18:48     ` Bjorn Helgaas
2012-02-06 18:55     ` Yinghai Lu
2012-02-06 18:55       ` Yinghai Lu
2012-02-10 20:51       ` Jesse Barnes [this message]
2012-02-10 23:40         ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 02/24] PCI: add busn inline helper Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 03/24] Make %pR could handle bus resource with domain Yinghai Lu
2012-02-05  6:57 ` [PATCH 04/24] PCI: Add busn_res operation functions Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-06 18:59   ` Bjorn Helgaas
2012-02-06 18:59     ` Bjorn Helgaas
2012-02-06 20:45     ` Yinghai Lu
2012-02-12 23:51       ` Bjorn Helgaas
2012-02-12 23:51         ` Bjorn Helgaas
2012-02-13  0:03         ` Yinghai Lu
2012-02-13  0:03           ` Yinghai Lu
2012-02-13  0:11           ` Bjorn Helgaas
2012-02-05  6:57 ` [PATCH 05/24] PCI: add /proc/iobusn Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 06/24] PCI: Add busn_res tracking in core Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-08 16:08   ` Bjorn Helgaas
2012-02-08 16:08     ` Bjorn Helgaas
2012-02-08 17:26     ` Yinghai Lu
2012-02-08 17:26       ` Yinghai Lu
2012-02-23 20:20       ` Jesse Barnes
2012-02-23 20:20         ` Jesse Barnes
2012-02-05  6:57 ` [PATCH 07/24] PCI, x86: Register busn_res for root buses Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 08/24] PCI, ia64: " Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 09/24] PCI, powerpc: " Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-08 15:58   ` Bjorn Helgaas
2012-02-08 15:58     ` Bjorn Helgaas
2012-02-08 17:31     ` Yinghai Lu
2012-02-08 17:31       ` Yinghai Lu
2012-02-08 22:02     ` Benjamin Herrenschmidt
2012-02-09 19:24       ` Bjorn Helgaas
2012-02-09 19:24         ` Bjorn Helgaas
2012-02-09 21:35         ` Benjamin Herrenschmidt
2012-02-09 21:35           ` Benjamin Herrenschmidt
2012-02-23 20:25           ` Jesse Barnes
2012-02-23 20:51             ` Bjorn Helgaas
2012-02-23 20:51               ` Bjorn Helgaas
2012-02-24 22:24               ` Jesse Barnes
2012-02-24 22:24                 ` Jesse Barnes
2012-02-25  7:47                 ` Yinghai Lu
2012-02-25  7:47                   ` Yinghai Lu
2012-02-27 22:44                   ` Bjorn Helgaas
2012-02-27 22:44                     ` Bjorn Helgaas
2012-02-05  6:57 ` [PATCH 10/24] PCI, parisc: " Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 11/24] PCI: Add pci_bus_extend/shrink_top() Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 12/24] PCI: Probe safe range that we can use for unassigned bridge Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 13/24] PCI: Strict checking of valid range for bridge Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 14/24] PCI: Allocate bus range instead of use max blindly Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-05  6:57 ` [PATCH 15/24] PCI: kill pci_fixup_parent_subordinate_busnr() Yinghai Lu
2012-02-05  6:57   ` Yinghai Lu
2012-02-05  6:58 ` [PATCH 16/24] PCI: Seperate child bus scanning to two passes overall Yinghai Lu
2012-02-05  6:58   ` Yinghai Lu
2012-02-05  6:58 ` [PATCH 17/24] pcmcia: remove workaround for fixing pci parent bus subordinate Yinghai Lu
2012-02-05  6:58   ` Yinghai Lu
2012-02-05  6:58 ` [PATCH 18/24] PCI: Double checking setting for bus register and bus struct Yinghai Lu
2012-02-05  6:58   ` Yinghai Lu
2012-02-05  6:58 ` [PATCH 19/24] PCI, pciehp: Remove not needed bus number range checking Yinghai Lu
2012-02-05  6:58 ` [PATCH 20/24] PCI, sys: Use device_type and attr_groups with pci dev Yinghai Lu
2012-02-05  6:58   ` Yinghai Lu
2012-02-05  6:58 ` [PATCH 21/24] PCI, sysfs: create rescan_bridge under /sys/.../pci/devices/... for pci bridges Yinghai Lu
2012-02-05  6:58 ` [PATCH 22/24] PCI: Add pci_bus_add_single_device() Yinghai Lu
2012-02-05  6:58   ` Yinghai Lu
2012-02-05  6:58 ` [PATCH 23/24] PCI: make pci_rescan_bus_bridge_resize use pci_scan_bridge instead Yinghai Lu
2012-02-05  6:58   ` Yinghai Lu
2012-02-05  6:58 ` [PATCH 24/24] PCI: clean up rescan_bus_bridge_resize Yinghai Lu
2012-02-05  6:58   ` Yinghai Lu

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