From mboxrd@z Thu Jan 1 00:00:00 1970 From: Russell King - ARM Linux Subject: Re: [PATCH] arm: Preserve TPIDRURW on context switch Date: Wed, 6 Feb 2013 22:51:50 +0000 Message-ID: <20130206225150.GL17833@n2100.arm.linux.org.uk> References: <5112DC7E.4020108@dawncrow.de> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Received: from caramon.arm.linux.org.uk ([78.32.30.218]:36983 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758218Ab3BFWwB (ORCPT ); Wed, 6 Feb 2013 17:52:01 -0500 Content-Disposition: inline In-Reply-To: <5112DC7E.4020108@dawncrow.de> Sender: linux-arch-owner@vger.kernel.org List-ID: To: =?iso-8859-1?Q?Andr=E9?= Hentschel Cc: linux-arch@vger.kernel.org, will.deacon@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Greg KH On Wed, Feb 06, 2013 at 11:43:10PM +0100, Andr=E9 Hentschel wrote: > There are more and more applications coming to WinRT, Wine could supp= ort them, > but mostly they expect to have the thread environment block (TEB) in = TPIDRURW. > This register must be preserved per thread instead of being cleared. I'd prefer this was done a little more sensitively to those CPUs where loads/stores are expensive, namely: > + > + @ preserve TPIDRURW register state > + get_tls2 r3, r4, r5 > + str r3, [r1, #TI_TP2_VALUE] > + ldr r3, [r2, #TI_TP2_VALUE] > + set_tls2 r3, r4, r5 those two loads/stores get omitted from the thread switching if the CPU doesn't support it. Do you think that's something you could do?