From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Subject: Re: [PATCH v6 4/5] MCS Lock: Barrier corrections
Date: Mon, 25 Nov 2013 15:51:06 -0800
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To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Tim Chen <tim.c.chen@linux.intel.com>, Peter Zijlstra <peterz@infradead.org>, Will Deacon <will.deacon@arm.com>, Ingo Molnar <mingo@elte.hu>, Andrew Morton <akpm@linux-foundation.org>, Thomas Gleixner <tglx@linutronix.de>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, linux-mm <linux-mm@kvack.org>, "linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>, Linus Torvalds <torvalds@linux-foundation.org>, Waiman Long <waiman.long@hp.com>, Andrea Arcangeli <aarcange@redhat.com>, Alex Shi <alex.shi@linaro.org>, Andi Kleen <andi@firstfloor.org>, Michel Lespinasse <walken@google.com>, Davidlohr Bueso <davidlohr.bueso@hp.com>, Matthew R Wilcox <matthew.r.wilcox@intel.com>, Dave Hansen <dave.hansen@intel.com>, Rik van Riel <riel@redhat.com>Peter
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On Mon, Nov 25, 2013 at 03:28:32PM -0800, H. Peter Anvin wrote:
> On 11/25/2013 02:58 PM, Tim Chen wrote:
> > 
> > Peter,
> > 
> > Want to check with you on Paul's example, 
> > where we are indeed writing and reading to the same
> > lock location when passing the lock on x86 with smp_store_release and
> > smp_load_acquire.  So the unlock and lock sequence looks like:
> > 
> >         CPU 0 (releasing)       CPU 1 (acquiring)
> >         -----                   -----
> >         ACCESS_ONCE(X) = 1;     while (ACCESS_ONCE(lock) == 1)
> >                                   continue;
> >         ACCESS_ONCE(lock) = 0;  
> >                                 r1 = ACCESS_ONCE(Y);
> > 
> 
> Here we can definitely state that the read from Y must have happened
> after X was set to 1 (assuming lock starts out as 1).
> 
> > observer CPU 2:
> > 
> >         CPU 2
> >         -----
> >         ACCESS_ONCE(Y) = 1;
> >         smp_mb();
> >         r2 = ACCESS_ONCE(X);
> > 
> > If the write and read to lock act as a full memory barrier, 
> > it would be impossible to
> > end up with (r1 == 0 && r2 == 0), correct?
> > 
> 
> It would be impossible to end up with r1 == 1 && r2 == 0, I presume
> that's what you meant.

Yes, that is the correct impossibility.  Thank you, Peter!

							Thanx, Paul

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