From: Peter Zijlstra <peterz@infradead.org>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: David Daney <ddaney@caviumnetworks.com>,
Ralf Baechle <ralf@linux-mips.org>,
"linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>,
linux-mips <linux-mips@linux-mips.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Paul McKenney <paulmck@linux.vnet.ibm.com>,
Will Deacon <will.deacon@arm.com>
Subject: Re: mips octeon memory model questions
Date: Tue, 4 Feb 2014 20:39:41 +0100 [thread overview]
Message-ID: <20140204193941.GD5002@laptop.programming.kicks-ass.net> (raw)
In-Reply-To: <CA+55aFwiuE+WbNLdeV8sGqZccoXkjg_VFOJ+xKMZUgbFP_sKZw@mail.gmail.com>
On Tue, Feb 04, 2014 at 11:16:58AM -0800, Linus Torvalds wrote:
> On Tue, Feb 4, 2014 at 11:05 AM, Peter Zijlstra
> >
> >> So writes move down, not up.
> >
> > Right, but the ll-sc store might move down over a later store.
>
> Unlikely. The thing is, in order for the sc to succeed, it has to
> already have hit the cache coherency domain (or at least reserved it -
> ie maybe the value is not actually *in* the cache, but the sc needs to
> have gotten exclusive access to the cacheline).
>
> So just how do you expect a later store (that is *after* the
> conditional branch that tests the result of the sc) to move up before
> it?
Ah, I completely overlooked the control dependency to the subsequent
store.
Yes, given that this makes sense.
next prev parent reply other threads:[~2014-02-04 19:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-04 18:41 mips octeon memory model questions Peter Zijlstra
2014-02-04 18:41 ` Peter Zijlstra
2014-02-04 18:58 ` Linus Torvalds
2014-02-04 19:05 ` Peter Zijlstra
2014-02-04 19:05 ` Peter Zijlstra
2014-02-04 19:16 ` Linus Torvalds
2014-02-04 19:39 ` Peter Zijlstra [this message]
2014-02-04 19:51 ` David Daney
2014-02-06 11:45 ` Peter Zijlstra
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