From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Zijlstra Subject: Re: mips octeon memory model questions Date: Tue, 4 Feb 2014 20:39:41 +0100 Message-ID: <20140204193941.GD5002@laptop.programming.kicks-ass.net> References: <20140204184150.GB5002@laptop.programming.kicks-ass.net> <20140204190535.GC5002@laptop.programming.kicks-ass.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from merlin.infradead.org ([205.233.59.134]:56434 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754870AbaBDTj5 (ORCPT ); Tue, 4 Feb 2014 14:39:57 -0500 Content-Disposition: inline In-Reply-To: Sender: linux-arch-owner@vger.kernel.org List-ID: To: Linus Torvalds Cc: David Daney , Ralf Baechle , "linux-arch@vger.kernel.org" , linux-mips , Linux Kernel Mailing List , Paul McKenney , Will Deacon On Tue, Feb 04, 2014 at 11:16:58AM -0800, Linus Torvalds wrote: > On Tue, Feb 4, 2014 at 11:05 AM, Peter Zijlstra > > > >> So writes move down, not up. > > > > Right, but the ll-sc store might move down over a later store. > > Unlikely. The thing is, in order for the sc to succeed, it has to > already have hit the cache coherency domain (or at least reserved it - > ie maybe the value is not actually *in* the cache, but the sc needs to > have gotten exclusive access to the cacheline). > > So just how do you expect a later store (that is *after* the > conditional branch that tests the result of the sc) to move up before > it? Ah, I completely overlooked the control dependency to the subsequent store. Yes, given that this makes sense.