From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Paul E. McKenney" Subject: Re: [RFC][PATCH 0/5] arch: atomic rework Date: Tue, 25 Feb 2014 21:23:06 -0800 Message-ID: <20140226052306.GD8264@linux.vnet.ibm.com> References: <20140224172110.GO8264@linux.vnet.ibm.com> <20140224185341.GU8264@linux.vnet.ibm.com> <20140224223701.GC8264@linux.vnet.ibm.com> <20140226001558.GY8264@linux.vnet.ibm.com> <530D6056.40305@redhat.com> Reply-To: paulmck@linux.vnet.ibm.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Content-Disposition: inline In-Reply-To: <530D6056.40305@redhat.com> To: Jeff Law Cc: Linus Torvalds , Torvald Riegel , Will Deacon , Peter Zijlstra , Ramana Radhakrishnan , David Howells , "linux-arch@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "akpm@linux-foundation.org" , "mingo@kernel.org" , "gcc@gcc.gnu.org" List-Id: linux-arch.vger.kernel.org On Tue, Feb 25, 2014 at 08:32:38PM -0700, Jeff Law wrote: > On 02/25/14 17:15, Paul E. McKenney wrote: > >>I have for the last several years been 100% convinced that the Intel > >>memory ordering is the right thing, and that people who like weak > >>memory ordering are wrong and should try to avoid reproducing if at > >>all possible. But given that we have memory orderings like power and > >>ARM, I don't actually see a sane way to get a good strong ordering. > >>You can teach compilers about cases like the above when they actually > >>see all the code and they could poison the value chain etc. But it > >>would be fairly painful, and once you cross object files (or even just > >>functions in the same compilation unit, for that matter), it goes from > >>painful to just "ridiculously not worth it". > > > >And I have indeed seen a post or two from you favoring stronger memory > >ordering over the past few years. ;-) > I couldn't agree more. > > > > >Are ARM and Power really the bad boys here? Or are they instead playing > >the role of the canary in the coal mine? > That's a question I've been struggling with recently as well. I > suspect they (arm, power) are going to be the outliers rather than > the canary. While the weaker model may give them some advantages WRT > scalability, I don't think it'll ultimately be enough to overcome > the difficulty in writing correct low level code for them. > > Regardless, they're here and we have to deal with them. Agreed... Thanx, Paul From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e35.co.us.ibm.com ([32.97.110.153]:46517 "EHLO e35.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751192AbaBZFXL (ORCPT ); Wed, 26 Feb 2014 00:23:11 -0500 Received: from /spool/local by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 25 Feb 2014 22:23:11 -0700 Date: Tue, 25 Feb 2014 21:23:06 -0800 From: "Paul E. McKenney" Subject: Re: [RFC][PATCH 0/5] arch: atomic rework Message-ID: <20140226052306.GD8264@linux.vnet.ibm.com> Reply-To: paulmck@linux.vnet.ibm.com References: <20140224172110.GO8264@linux.vnet.ibm.com> <20140224185341.GU8264@linux.vnet.ibm.com> <20140224223701.GC8264@linux.vnet.ibm.com> <20140226001558.GY8264@linux.vnet.ibm.com> <530D6056.40305@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <530D6056.40305@redhat.com> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Jeff Law Cc: Linus Torvalds , Torvald Riegel , Will Deacon , Peter Zijlstra , Ramana Radhakrishnan , David Howells , "linux-arch@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "akpm@linux-foundation.org" , "mingo@kernel.org" , "gcc@gcc.gnu.org" Message-ID: <20140226052306.1J6BOT5cnU9oPT3I1nTQuBAvpgwLm0rmRjBrnY5ME6c@z> On Tue, Feb 25, 2014 at 08:32:38PM -0700, Jeff Law wrote: > On 02/25/14 17:15, Paul E. McKenney wrote: > >>I have for the last several years been 100% convinced that the Intel > >>memory ordering is the right thing, and that people who like weak > >>memory ordering are wrong and should try to avoid reproducing if at > >>all possible. But given that we have memory orderings like power and > >>ARM, I don't actually see a sane way to get a good strong ordering. > >>You can teach compilers about cases like the above when they actually > >>see all the code and they could poison the value chain etc. But it > >>would be fairly painful, and once you cross object files (or even just > >>functions in the same compilation unit, for that matter), it goes from > >>painful to just "ridiculously not worth it". > > > >And I have indeed seen a post or two from you favoring stronger memory > >ordering over the past few years. ;-) > I couldn't agree more. > > > > >Are ARM and Power really the bad boys here? Or are they instead playing > >the role of the canary in the coal mine? > That's a question I've been struggling with recently as well. I > suspect they (arm, power) are going to be the outliers rather than > the canary. While the weaker model may give them some advantages WRT > scalability, I don't think it'll ultimately be enough to overcome > the difficulty in writing correct low level code for them. > > Regardless, they're here and we have to deal with them. Agreed... Thanx, Paul