From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH 1/5] atomics: add acquire/release/relaxed variants of some atomic operations Date: Tue, 14 Jul 2015 16:55:06 +0100 Message-ID: <20150714155500.GQ16213@arm.com> References: <1436790687-11984-1-git-send-email-will.deacon@arm.com> <1436790687-11984-2-git-send-email-will.deacon@arm.com> <20150714102511.GI19282@twins.programming.kicks-ass.net> <20150714103220.GB16213@arm.com> <20150714105837.GJ19282@twins.programming.kicks-ass.net> <20150714110811.GE16213@arm.com> <20150714112420.GK3644@twins.programming.kicks-ass.net> <20150714113147.GF16213@arm.com> <20150714113801.GK19282@twins.programming.kicks-ass.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20150714113801.GK19282@twins.programming.kicks-ass.net> Sender: linux-kernel-owner@vger.kernel.org To: Peter Zijlstra Cc: "linux-arch@vger.kernel.org" , "Waiman.Long@hp.com" , "linux-kernel@vger.kernel.org" , "paulmck@linux.vnet.ibm.com" List-Id: linux-arch.vger.kernel.org On Tue, Jul 14, 2015 at 12:38:01PM +0100, Peter Zijlstra wrote: > On Tue, Jul 14, 2015 at 12:31:47PM +0100, Will Deacon wrote: > > #ifndef atomic_add > > #define atomic_add(args...) (void)atomic_add_return_relaxed(args); > > > > It would mean a new architecture only has to define a barrier instruction > > and a handful of relaxed atomics for a bare-minimum atomic.h avoiding > > spinlocks. > > Look at include/asm-generic/atomic.h, all you need is a cmpxchg(). > > We could easily change that to be cmpxchg_relaxed() and a few barriers. Ok, I'll leave that part for now and implement your original suggestion as a starting point. Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com ([217.140.101.70]:34864 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752285AbbGNPzK (ORCPT ); Tue, 14 Jul 2015 11:55:10 -0400 Date: Tue, 14 Jul 2015 16:55:06 +0100 From: Will Deacon Subject: Re: [PATCH 1/5] atomics: add acquire/release/relaxed variants of some atomic operations Message-ID: <20150714155500.GQ16213@arm.com> References: <1436790687-11984-1-git-send-email-will.deacon@arm.com> <1436790687-11984-2-git-send-email-will.deacon@arm.com> <20150714102511.GI19282@twins.programming.kicks-ass.net> <20150714103220.GB16213@arm.com> <20150714105837.GJ19282@twins.programming.kicks-ass.net> <20150714110811.GE16213@arm.com> <20150714112420.GK3644@twins.programming.kicks-ass.net> <20150714113147.GF16213@arm.com> <20150714113801.GK19282@twins.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150714113801.GK19282@twins.programming.kicks-ass.net> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Peter Zijlstra Cc: "linux-arch@vger.kernel.org" , "Waiman.Long@hp.com" , "linux-kernel@vger.kernel.org" , "paulmck@linux.vnet.ibm.com" Message-ID: <20150714155506.xC5sEvntnYwu_hz0OM800nrhIhMWl5Y520iIDRCPvMs@z> On Tue, Jul 14, 2015 at 12:38:01PM +0100, Peter Zijlstra wrote: > On Tue, Jul 14, 2015 at 12:31:47PM +0100, Will Deacon wrote: > > #ifndef atomic_add > > #define atomic_add(args...) (void)atomic_add_return_relaxed(args); > > > > It would mean a new architecture only has to define a barrier instruction > > and a handful of relaxed atomics for a bare-minimum atomic.h avoiding > > spinlocks. > > Look at include/asm-generic/atomic.h, all you need is a cmpxchg(). > > We could easily change that to be cmpxchg_relaxed() and a few barriers. Ok, I'll leave that part for now and implement your original suggestion as a starting point. Will