From: Will Deacon <will.deacon@arm.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: "linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>,
"Waiman.Long@hp.com" <Waiman.Long@hp.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"paulmck@linux.vnet.ibm.com" <paulmck@linux.vnet.ibm.com>
Subject: Re: [PATCH v2 5/7] locking/qrwlock: make use of acquire/release/relaxed atomics
Date: Thu, 16 Jul 2015 19:13:27 +0100 [thread overview]
Message-ID: <20150716181327.GT26390@arm.com> (raw)
In-Reply-To: <20150716165903.GA19282@twins.programming.kicks-ass.net>
On Thu, Jul 16, 2015 at 05:59:03PM +0100, Peter Zijlstra wrote:
> On Thu, Jul 16, 2015 at 04:32:36PM +0100, Will Deacon wrote:
> > @@ -130,8 +130,7 @@ static inline void queued_read_unlock(struct qrwlock *lock)
> > /*
> > * Atomically decrement the reader count
> > */
> > - smp_mb__before_atomic();
> > - atomic_sub(_QR_BIAS, &lock->cnts);
> > + (void)atomic_sub_return_release(_QR_BIAS, &lock->cnts);
> > }
> >
> > /**
>
> This one will actually cause different code on x86; I think its still
> fine though. LOCK XADD should not be (much) slower than LOCK SUB.
Yeah, I wondered whether introduced atomic_sub_release etc was worth the
hassle and decided against it for now.
> > diff --git a/kernel/locking/qrwlock.c b/kernel/locking/qrwlock.c
> > index a71bb3541880..879c8fab7bea 100644
> > --- a/kernel/locking/qrwlock.c
> > +++ b/kernel/locking/qrwlock.c
> > @@ -36,7 +36,7 @@ rspin_until_writer_unlock(struct qrwlock *lock, u32 cnts)
> > {
> > while ((cnts & _QW_WMASK) == _QW_LOCKED) {
> > cpu_relax_lowlatency();
> > - cnts = smp_load_acquire((u32 *)&lock->cnts);
> > + cnts = atomic_read_acquire(&lock->cnts);
> > }
> > }
>
> It might make sense to add comments to the users of this function that
> actually rely on the _acquire semantics, I had to double check that :-)
Good point, I'll add those.
> But otherwise that all looks good.
Cheers. I'll send a v3 next week with your comments addressed. Pending
any objection, I guess this could be merged via -tip with the exception
of the ARM patch? FWIW, I plan to port arm64 once I've got my pending
asm/atomic.h rework queued.
Will
next prev parent reply other threads:[~2015-07-16 18:13 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-16 15:32 [PATCH v2 0/7] Add generic support for relaxed atomics Will Deacon
2015-07-16 15:32 ` Will Deacon
2015-07-16 15:32 ` [PATCH v2 1/7] atomics: add acquire/release/relaxed variants of some atomic operations Will Deacon
2015-07-16 15:32 ` Will Deacon
2015-07-17 0:07 ` Waiman Long
2015-07-17 9:40 ` Will Deacon
2015-07-17 17:19 ` Waiman Long
2015-07-17 17:19 ` Waiman Long
2015-07-17 17:30 ` Will Deacon
2015-07-16 15:32 ` [PATCH v2 2/7] asm-generic: rework atomic-long.h to avoid bulk code duplication Will Deacon
2015-07-16 15:32 ` Will Deacon
2015-07-16 15:32 ` [PATCH v2 3/7] asm-generic: add relaxed/acquire/release variants for atomic_long_t Will Deacon
2015-07-16 15:32 ` Will Deacon
2015-07-16 15:32 ` [PATCH v2 4/7] lockref: remove homebrew cmpxchg64_relaxed macro definition Will Deacon
2015-07-16 15:32 ` Will Deacon
2015-07-16 16:48 ` Peter Zijlstra
2015-07-16 17:00 ` Will Deacon
2015-07-16 15:32 ` [PATCH v2 5/7] locking/qrwlock: make use of acquire/release/relaxed atomics Will Deacon
2015-07-16 15:32 ` Will Deacon
2015-07-16 16:59 ` Peter Zijlstra
2015-07-16 18:13 ` Will Deacon [this message]
2015-07-16 18:13 ` Will Deacon
2015-07-16 15:32 ` [PATCH v2 6/7] include/llist: use linux/atomic.h instead of asm/cmpxchg.h Will Deacon
2015-07-16 15:32 ` Will Deacon
2015-07-16 15:32 ` [PATCH v2 7/7] ARM: atomics: define our SMP atomics in terms of _relaxed operations Will Deacon
2015-07-16 15:32 ` Will Deacon
2015-07-16 20:40 ` Waiman Long
2015-07-16 21:08 ` Peter Zijlstra
2015-07-16 21:08 ` Peter Zijlstra
2015-07-17 0:00 ` Waiman Long
2015-07-17 9:35 ` Will Deacon
2015-07-17 9:35 ` Will Deacon
2015-07-17 17:17 ` Waiman Long
2015-07-17 17:17 ` Waiman Long
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