From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: Linus Torvalds <torvalds@linux-foundation.org>,
Andrew Morton <akpm@linux-foundation.org>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Arnd Bergmann <arnd@arndb.de>,
"H. Peter Anvin" <hpa@zytor.com>
Cc: Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Andy Lutomirski <luto@amacapital.net>,
Michal Hocko <mhocko@suse.com>,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
linux-kernel@vger.kernel.org,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Subject: [PATCHv2 1/7] x86/cpufeature: Add 5-level paging detection
Date: Thu, 9 Mar 2017 17:24:02 +0300 [thread overview]
Message-ID: <20170309142408.2868-2-kirill.shutemov@linux.intel.com> (raw)
In-Reply-To: <20170309142408.2868-1-kirill.shutemov@linux.intel.com>
Look for 'la57' in /proc/cpuinfo to see if your machine supports 5-level
paging.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Acked-by: Michal Hocko <mhocko@suse.com>
---
arch/x86/include/asm/cpufeatures.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 4e7772387c6e..b04bb6dfed7f 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -289,7 +289,8 @@
#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
-#define X86_FEATURE_RDPID (16*32+ 22) /* RDPID instruction */
+#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
+#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */
--
2.11.0
--
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WARNING: multiple messages have this Message-ID (diff)
From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: Linus Torvalds <torvalds@linux-foundation.org>,
Andrew Morton <akpm@linux-foundation.org>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Arnd Bergmann <arnd@arndb.de>,
"H. Peter Anvin" <hpa@zytor.com>
Cc: Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Andy Lutomirski <luto@amacapital.net>,
Michal Hocko <mhocko@suse.com>,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
linux-kernel@vger.kernel.org,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Subject: [PATCHv2 1/7] x86/cpufeature: Add 5-level paging detection
Date: Thu, 9 Mar 2017 17:24:02 +0300 [thread overview]
Message-ID: <20170309142408.2868-2-kirill.shutemov@linux.intel.com> (raw)
Message-ID: <20170309142402.6iR0TOLKrePbdFtF5LBscN1XhEGfgYAZ5VZEdEmXwjM@z> (raw)
In-Reply-To: <20170309142408.2868-1-kirill.shutemov@linux.intel.com>
Look for 'la57' in /proc/cpuinfo to see if your machine supports 5-level
paging.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Acked-by: Michal Hocko <mhocko@suse.com>
---
arch/x86/include/asm/cpufeatures.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 4e7772387c6e..b04bb6dfed7f 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -289,7 +289,8 @@
#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
-#define X86_FEATURE_RDPID (16*32+ 22) /* RDPID instruction */
+#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
+#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */
--
2.11.0
next prev parent reply other threads:[~2017-03-09 14:24 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-09 14:24 [PATCHv2 0/7] 5-level paging: prepare generic code Kirill A. Shutemov
2017-03-09 14:24 ` Kirill A. Shutemov
2017-03-09 14:24 ` Kirill A. Shutemov [this message]
2017-03-09 14:24 ` [PATCHv2 1/7] x86/cpufeature: Add 5-level paging detection Kirill A. Shutemov
2017-03-09 14:24 ` [PATCHv2 2/7] asm-generic: introduce 5level-fixup.h Kirill A. Shutemov
2017-03-09 14:24 ` Kirill A. Shutemov
2017-03-09 14:24 ` [PATCHv2 3/7] asm-generic: introduce __ARCH_USE_5LEVEL_HACK Kirill A. Shutemov
2017-03-09 14:24 ` Kirill A. Shutemov
2017-03-09 14:24 ` [PATCHv2 4/7] arch, mm: convert all architectures to use 5level-fixup.h Kirill A. Shutemov
2017-03-09 14:24 ` Kirill A. Shutemov
2017-03-09 14:24 ` [PATCHv2 5/7] asm-generic: introduce <asm-generic/pgtable-nop4d.h> Kirill A. Shutemov
2017-03-09 14:24 ` Kirill A. Shutemov
2017-03-09 14:24 ` [PATCHv2 6/7] mm: convert generic code to 5-level paging Kirill A. Shutemov
2017-03-09 14:24 ` Kirill A. Shutemov
2017-03-14 16:14 ` [PATCHv2,6/7] " Heiko Stübner
2017-03-14 17:06 ` Kirill A. Shutemov
2017-03-14 17:06 ` Kirill A. Shutemov
2017-03-14 18:55 ` Heiko Stübner
2017-03-14 18:55 ` Heiko Stübner
2017-03-09 14:24 ` [PATCHv2 7/7] mm: introduce __p4d_alloc() Kirill A. Shutemov
2017-03-09 14:24 ` Kirill A. Shutemov
2017-03-09 20:26 ` [PATCHv2 0/7] 5-level paging: prepare generic code Linus Torvalds
2017-03-09 20:26 ` Linus Torvalds
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