From: Ingo Molnar <mingo@kernel.org>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
Andrew Morton <akpm@linux-foundation.org>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Andy Lutomirski <luto@amacapital.net>,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/8] x86/boot/64: Add support of additional page table level during early boot
Date: Tue, 11 Apr 2017 09:02:03 +0200 [thread overview]
Message-ID: <20170411070203.GA14621@gmail.com> (raw)
In-Reply-To: <20170406140106.78087-4-kirill.shutemov@linux.intel.com>
* Kirill A. Shutemov <kirill.shutemov@linux.intel.com> wrote:
> This patch adds support for 5-level paging during early boot.
> It generalizes boot for 4- and 5-level paging on 64-bit systems with
> compile-time switch between them.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> ---
> arch/x86/boot/compressed/head_64.S | 23 ++++++++++++---
> arch/x86/include/asm/pgtable_64.h | 2 ++
> arch/x86/include/uapi/asm/processor-flags.h | 2 ++
> arch/x86/kernel/head64.c | 44 +++++++++++++++++++++++++----
> arch/x86/kernel/head_64.S | 29 +++++++++++++++----
> 5 files changed, 85 insertions(+), 15 deletions(-)
>
> diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
> index d2ae1f821e0c..3ed26769810b 100644
> --- a/arch/x86/boot/compressed/head_64.S
> +++ b/arch/x86/boot/compressed/head_64.S
> @@ -122,9 +122,12 @@ ENTRY(startup_32)
> addl %ebp, gdt+2(%ebp)
> lgdt gdt(%ebp)
>
> - /* Enable PAE mode */
> + /* Enable PAE and LA57 mode */
> movl %cr4, %eax
> orl $X86_CR4_PAE, %eax
> +#ifdef CONFIG_X86_5LEVEL
> + orl $X86_CR4_LA57, %eax
> +#endif
> movl %eax, %cr4
>
> /*
> @@ -136,13 +139,24 @@ ENTRY(startup_32)
> movl $(BOOT_INIT_PGT_SIZE/4), %ecx
> rep stosl
>
> + xorl %edx, %edx
> +
> + /* Build Top Level */
> + leal pgtable(%ebx,%edx,1), %edi
> + leal 0x1007 (%edi), %eax
> + movl %eax, 0(%edi)
> +
> +#ifdef CONFIG_X86_5LEVEL
> /* Build Level 4 */
> - leal pgtable + 0(%ebx), %edi
> + addl $0x1000, %edx
> + leal pgtable(%ebx,%edx), %edi
> leal 0x1007 (%edi), %eax
> movl %eax, 0(%edi)
> +#endif
>
> /* Build Level 3 */
> - leal pgtable + 0x1000(%ebx), %edi
> + addl $0x1000, %edx
> + leal pgtable(%ebx,%edx), %edi
> leal 0x1007(%edi), %eax
> movl $4, %ecx
> 1: movl %eax, 0x00(%edi)
> @@ -152,7 +166,8 @@ ENTRY(startup_32)
> jnz 1b
>
> /* Build Level 2 */
> - leal pgtable + 0x2000(%ebx), %edi
> + addl $0x1000, %edx
> + leal pgtable(%ebx,%edx), %edi
> movl $0x00000183, %eax
> movl $2048, %ecx
> 1: movl %eax, 0(%edi)
I realize that you had difficulties converting this to C, but it's not going to
get any easier in the future either, with one more paging mode/level added!
If you are stuck on where it breaks I'd suggest doing it gradually: first add a
trivial .c, build and link it in and call it separately. Then once that works,
move functionality from asm to C step by step and test it at every step.
I've applied the first two patches of this series, but we really should convert
this assembly bit to C too.
Thanks,
Ingo
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WARNING: multiple messages have this Message-ID (diff)
From: Ingo Molnar <mingo@kernel.org>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
Andrew Morton <akpm@linux-foundation.org>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Andy Lutomirski <luto@amacapital.net>,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/8] x86/boot/64: Add support of additional page table level during early boot
Date: Tue, 11 Apr 2017 09:02:03 +0200 [thread overview]
Message-ID: <20170411070203.GA14621@gmail.com> (raw)
Message-ID: <20170411070203.t5cxkBR-ImdRbJSP76tYRvX2uWhe1k2Z4bbzOgII_mk@z> (raw)
In-Reply-To: <20170406140106.78087-4-kirill.shutemov@linux.intel.com>
* Kirill A. Shutemov <kirill.shutemov@linux.intel.com> wrote:
> This patch adds support for 5-level paging during early boot.
> It generalizes boot for 4- and 5-level paging on 64-bit systems with
> compile-time switch between them.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> ---
> arch/x86/boot/compressed/head_64.S | 23 ++++++++++++---
> arch/x86/include/asm/pgtable_64.h | 2 ++
> arch/x86/include/uapi/asm/processor-flags.h | 2 ++
> arch/x86/kernel/head64.c | 44 +++++++++++++++++++++++++----
> arch/x86/kernel/head_64.S | 29 +++++++++++++++----
> 5 files changed, 85 insertions(+), 15 deletions(-)
>
> diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
> index d2ae1f821e0c..3ed26769810b 100644
> --- a/arch/x86/boot/compressed/head_64.S
> +++ b/arch/x86/boot/compressed/head_64.S
> @@ -122,9 +122,12 @@ ENTRY(startup_32)
> addl %ebp, gdt+2(%ebp)
> lgdt gdt(%ebp)
>
> - /* Enable PAE mode */
> + /* Enable PAE and LA57 mode */
> movl %cr4, %eax
> orl $X86_CR4_PAE, %eax
> +#ifdef CONFIG_X86_5LEVEL
> + orl $X86_CR4_LA57, %eax
> +#endif
> movl %eax, %cr4
>
> /*
> @@ -136,13 +139,24 @@ ENTRY(startup_32)
> movl $(BOOT_INIT_PGT_SIZE/4), %ecx
> rep stosl
>
> + xorl %edx, %edx
> +
> + /* Build Top Level */
> + leal pgtable(%ebx,%edx,1), %edi
> + leal 0x1007 (%edi), %eax
> + movl %eax, 0(%edi)
> +
> +#ifdef CONFIG_X86_5LEVEL
> /* Build Level 4 */
> - leal pgtable + 0(%ebx), %edi
> + addl $0x1000, %edx
> + leal pgtable(%ebx,%edx), %edi
> leal 0x1007 (%edi), %eax
> movl %eax, 0(%edi)
> +#endif
>
> /* Build Level 3 */
> - leal pgtable + 0x1000(%ebx), %edi
> + addl $0x1000, %edx
> + leal pgtable(%ebx,%edx), %edi
> leal 0x1007(%edi), %eax
> movl $4, %ecx
> 1: movl %eax, 0x00(%edi)
> @@ -152,7 +166,8 @@ ENTRY(startup_32)
> jnz 1b
>
> /* Build Level 2 */
> - leal pgtable + 0x2000(%ebx), %edi
> + addl $0x1000, %edx
> + leal pgtable(%ebx,%edx), %edi
> movl $0x00000183, %eax
> movl $2048, %ecx
> 1: movl %eax, 0(%edi)
I realize that you had difficulties converting this to C, but it's not going to
get any easier in the future either, with one more paging mode/level added!
If you are stuck on where it breaks I'd suggest doing it gradually: first add a
trivial .c, build and link it in and call it separately. Then once that works,
move functionality from asm to C step by step and test it at every step.
I've applied the first two patches of this series, but we really should convert
this assembly bit to C too.
Thanks,
Ingo
next prev parent reply other threads:[~2017-04-11 7:02 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-06 14:00 [PATCH 0/8] x86: 5-level paging enabling for v4.12, Part 4 Kirill A. Shutemov
2017-04-06 14:00 ` Kirill A. Shutemov
2017-04-06 14:00 ` [PATCH 1/8] x86/boot/64: Rewrite startup_64 in C Kirill A. Shutemov
2017-04-06 14:00 ` Kirill A. Shutemov
2017-04-06 14:01 ` [PATCH 2/8] x86/boot/64: Rename init_level4_pgt and early_level4_pgt Kirill A. Shutemov
2017-04-06 14:01 ` [PATCH 3/8] x86/boot/64: Add support of additional page table level during early boot Kirill A. Shutemov
2017-04-06 14:01 ` Kirill A. Shutemov
2017-04-11 7:02 ` Ingo Molnar [this message]
2017-04-11 7:02 ` Ingo Molnar
2017-04-11 10:51 ` Kirill A. Shutemov
2017-04-11 10:51 ` Kirill A. Shutemov
2017-04-11 11:28 ` Ingo Molnar
2017-04-11 11:28 ` Ingo Molnar
2017-04-11 11:46 ` Kirill A. Shutemov
2017-04-11 11:46 ` Kirill A. Shutemov
2017-04-11 14:09 ` Andi Kleen
2017-04-12 10:18 ` Kirill A. Shutemov
2017-04-17 10:32 ` Ingo Molnar
2017-04-17 10:32 ` Ingo Molnar
2017-04-18 8:59 ` Kirill A. Shutemov
2017-04-18 8:59 ` Kirill A. Shutemov
2017-04-18 10:15 ` Kirill A. Shutemov
2017-04-18 11:10 ` Kirill A. Shutemov
2017-04-18 11:10 ` Kirill A. Shutemov
2017-04-06 14:01 ` [PATCH 4/8] x86/mm: Add sync_global_pgds() for configuration with 5-level paging Kirill A. Shutemov
2017-04-06 14:01 ` Kirill A. Shutemov
2017-04-06 14:01 ` [PATCH 5/8] x86/mm: Make kernel_physical_mapping_init() support " Kirill A. Shutemov
2017-04-06 14:01 ` Kirill A. Shutemov
2017-04-06 14:01 ` [PATCH 6/8] x86/mm: Add support for 5-level paging for KASLR Kirill A. Shutemov
2017-04-06 14:01 ` Kirill A. Shutemov
2017-04-06 14:01 ` [PATCH 7/8] x86: Enable 5-level paging support Kirill A. Shutemov
2017-04-06 14:01 ` Kirill A. Shutemov
2017-04-06 14:52 ` Juergen Gross
2017-04-06 15:24 ` Kirill A. Shutemov
2017-04-06 15:56 ` Juergen Gross
2017-04-06 14:01 ` [PATCH 8/8] x86/mm: Allow to have userspace mappings above 47-bits Kirill A. Shutemov
2017-04-06 14:01 ` Kirill A. Shutemov
2017-04-06 18:43 ` Dmitry Safonov
2017-04-06 19:15 ` Dmitry Safonov
2017-04-06 23:21 ` Kirill A. Shutemov
2017-04-06 23:24 ` [PATCHv2 " Kirill A. Shutemov
2017-04-06 23:24 ` Kirill A. Shutemov
2017-04-07 11:32 ` Dmitry Safonov
2017-04-07 15:44 ` [PATCHv3 " Kirill A. Shutemov
2017-04-07 16:37 ` Dmitry Safonov
2017-04-13 11:30 ` [PATCHv4 0/9] x86: 5-level paging enabling for v4.12, Part 4 Kirill A. Shutemov
2017-04-13 11:30 ` Kirill A. Shutemov
2017-04-13 11:30 ` [PATCHv4 1/9] x86/asm: Fix comment in return_from_SYSCALL_64 Kirill A. Shutemov
2017-04-13 11:30 ` Kirill A. Shutemov
2017-04-13 11:30 ` [PATCHv4 2/9] x86/boot/64: Rewrite startup_64 in C Kirill A. Shutemov
2017-04-13 11:30 ` Kirill A. Shutemov
2017-04-13 11:30 ` [PATCHv4 3/9] x86/boot/64: Rename init_level4_pgt and early_level4_pgt Kirill A. Shutemov
2017-04-13 11:30 ` Kirill A. Shutemov
2017-04-13 11:30 ` [PATCHv4 4/9] x86/boot/64: Add support of additional page table level during early boot Kirill A. Shutemov
2017-04-13 11:30 ` Kirill A. Shutemov
2017-04-13 11:30 ` [PATCHv4 5/9] x86/mm: Add sync_global_pgds() for configuration with 5-level paging Kirill A. Shutemov
2017-04-13 11:30 ` Kirill A. Shutemov
2017-04-13 11:30 ` [PATCHv4 6/9] x86/mm: Make kernel_physical_mapping_init() support " Kirill A. Shutemov
2017-04-13 11:30 ` Kirill A. Shutemov
2017-04-13 11:30 ` [PATCHv4 7/9] x86/mm: Add support for 5-level paging for KASLR Kirill A. Shutemov
2017-04-13 11:30 ` Kirill A. Shutemov
2017-04-13 11:30 ` [PATCHv4 8/9] x86: Enable 5-level paging support Kirill A. Shutemov
2017-04-13 11:30 ` Kirill A. Shutemov
2017-04-13 11:30 ` [PATCHv4 9/9] x86/mm: Allow to have userspace mappings above 47-bits Kirill A. Shutemov
2017-04-13 11:30 ` Kirill A. Shutemov
2017-04-07 10:06 ` [PATCH 8/8] " Dmitry Safonov
2017-04-07 13:35 ` Anshuman Khandual
2017-04-07 13:35 ` Anshuman Khandual
2017-04-07 15:59 ` Kirill A. Shutemov
2017-04-07 15:59 ` Kirill A. Shutemov
2017-04-07 16:09 ` hpa
2017-04-07 16:09 ` hpa
2017-04-07 16:20 ` Kirill A. Shutemov
2017-04-12 10:41 ` Michael Ellerman
2017-04-12 11:11 ` Kirill A. Shutemov
2017-04-12 11:11 ` Kirill A. Shutemov
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