From: "Kirill A. Shutemov" <kirill@shutemov.name> To: Michael Ellerman <mpe@ellerman.id.au> Cc: Anshuman Khandual <khandual@linux.vnet.ibm.com>, "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>, Linus Torvalds <torvalds@linux-foundation.org>, Andrew Morton <akpm@linux-foundation.org>, x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>, Andi Kleen <ak@linux.intel.com>, Dave Hansen <dave.hansen@intel.com>, Andy Lutomirski <luto@amacapital.net>, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Dmitry Safonov <dsafonov@virtuozzo.com>, "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> Subject: Re: [PATCH 8/8] x86/mm: Allow to have userspace mappings above 47-bits Date: Wed, 12 Apr 2017 14:11:57 +0300 [thread overview] Message-ID: <20170412111157.h6tjryt7jbum4tfg@node.shutemov.name> (raw) In-Reply-To: <87wpap6h7q.fsf@concordia.ellerman.id.au> On Wed, Apr 12, 2017 at 08:41:29PM +1000, Michael Ellerman wrote: > Hi Kirill, > > I'm interested in this because we're doing pretty much the same thing on > powerpc at the moment, and I want to make sure x86 & powerpc end up with > compatible behaviour. > > "Kirill A. Shutemov" <kirill@shutemov.name> writes: > > On Fri, Apr 07, 2017 at 07:05:26PM +0530, Anshuman Khandual wrote: > >> On 04/06/2017 07:31 PM, Kirill A. Shutemov wrote: > >> > On x86, 5-level paging enables 56-bit userspace virtual address space. > >> > Not all user space is ready to handle wide addresses. It's known that > >> > at least some JIT compilers use higher bits in pointers to encode their > >> > information. It collides with valid pointers with 5-level paging and > >> > leads to crashes. > >> > > >> > To mitigate this, we are not going to allocate virtual address space > >> > above 47-bit by default. > >> > >> I am wondering if the commitment of virtual space range to the > >> user space is kind of an API which needs to be maintained there > >> after. If that is the case then we need to have some plans when > >> increasing it from the current level. > > > > I don't think we should ever enable full address space for all > > applications. There's no point. > > > > /bin/true doesn't need more than 64TB of virtual memory. > > And I hope never will. > > > > By increasing virtual address space for everybody we will pay (assuming > > current page table format) at least one extra page per process for moving > > stack at very end of address space. > > That assumes the current layout though, it could be different. True. > > Yes, you can gain something in security by having more bits for ASLR, but > > I don't think it worth the cost. > > It may not be worth the cost now, for you, but that trade off will be > different for other people and at other times. > > So I think it's quite likely some folks will be interested in the full > address range for ASLR. We always can extend interface if/when userspace demand materialize. Let's not invent interfaces unless we're sure there's demand. > >> expanding the address range next time around. I think we need > >> to have a plan for this and particularly around 'hint' mechanism > >> and whether it should be decided per mmap() request or at the > >> task level. > > > > I think the reasonable way for an application to claim it's 63-bit clean > > is to make allocations with (void *)-1 as hint address. > > I do like the simplicity of that. > > But I wouldn't be surprised if some (crappy) code out there already > passes an address of -1. Probably it won't break if it starts getting > high addresses, but who knows. To make an application break we need two thing: - it sets hint address to -1 by mistake; - it uses upper bit to encode its info; I would be surprise if such combination exists in real world. But let me know if you have any particular code in mind. > An alternative would be to only interpret the hint as requesting a large > address if it's >= 64TB && < TASK_SIZE_MAX. Nope. That doesn't work if you take into accounting further extension of the address space. Consider extension x86 to 6-level page tables. User-space has 63-bit address space. TASK_SIZE_MAX is bumped to (1UL << 63) - PAGE_SIZE. An application wants access to full address space. It gets recompiled using new TASK_SIZE_MAX as hint address. And everything works fine. But only on machine with 6-level paging enabled. If we run the same application binary on machine with older kernel and 5-level paging, the application will get access to only 47-bit address space, not 56-bit, as hint address is more than TASK_SIZE_MAX in this configuration. > If we're really worried about breaking userspace then a new MMAP flag > seems like the safest option? > > I don't feel particularly strongly about any option, but like I said my > main concern is that x86 & powerpc end up with the same behaviour. > > And whatever we end up with someone will need to do an update to the man > page for mmap. Sure. -- Kirill A. Shutemov -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@kvack.org"> email@kvack.org </a>
WARNING: multiple messages have this Message-ID (diff)
From: "Kirill A. Shutemov" <kirill@shutemov.name> To: Michael Ellerman <mpe@ellerman.id.au> Cc: Anshuman Khandual <khandual@linux.vnet.ibm.com>, "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>, Linus Torvalds <torvalds@linux-foundation.org>, Andrew Morton <akpm@linux-foundation.org>, x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>, Andi Kleen <ak@linux.intel.com>, Dave Hansen <dave.hansen@intel.com>, Andy Lutomirski <luto@amacapital.net>, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Dmitry Safonov <dsafonov@virtuozzo.com>, "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> Subject: Re: [PATCH 8/8] x86/mm: Allow to have userspace mappings above 47-bits Date: Wed, 12 Apr 2017 14:11:57 +0300 [thread overview] Message-ID: <20170412111157.h6tjryt7jbum4tfg@node.shutemov.name> (raw) Message-ID: <20170412111157.XxfZ2dy5mbdOA6jX_m0wsuPQB3Ve-Cp4Bq5w23eC4gM@z> (raw) In-Reply-To: <87wpap6h7q.fsf@concordia.ellerman.id.au> On Wed, Apr 12, 2017 at 08:41:29PM +1000, Michael Ellerman wrote: > Hi Kirill, > > I'm interested in this because we're doing pretty much the same thing on > powerpc at the moment, and I want to make sure x86 & powerpc end up with > compatible behaviour. > > "Kirill A. Shutemov" <kirill@shutemov.name> writes: > > On Fri, Apr 07, 2017 at 07:05:26PM +0530, Anshuman Khandual wrote: > >> On 04/06/2017 07:31 PM, Kirill A. Shutemov wrote: > >> > On x86, 5-level paging enables 56-bit userspace virtual address space. > >> > Not all user space is ready to handle wide addresses. It's known that > >> > at least some JIT compilers use higher bits in pointers to encode their > >> > information. It collides with valid pointers with 5-level paging and > >> > leads to crashes. > >> > > >> > To mitigate this, we are not going to allocate virtual address space > >> > above 47-bit by default. > >> > >> I am wondering if the commitment of virtual space range to the > >> user space is kind of an API which needs to be maintained there > >> after. If that is the case then we need to have some plans when > >> increasing it from the current level. > > > > I don't think we should ever enable full address space for all > > applications. There's no point. > > > > /bin/true doesn't need more than 64TB of virtual memory. > > And I hope never will. > > > > By increasing virtual address space for everybody we will pay (assuming > > current page table format) at least one extra page per process for moving > > stack at very end of address space. > > That assumes the current layout though, it could be different. True. > > Yes, you can gain something in security by having more bits for ASLR, but > > I don't think it worth the cost. > > It may not be worth the cost now, for you, but that trade off will be > different for other people and at other times. > > So I think it's quite likely some folks will be interested in the full > address range for ASLR. We always can extend interface if/when userspace demand materialize. Let's not invent interfaces unless we're sure there's demand. > >> expanding the address range next time around. I think we need > >> to have a plan for this and particularly around 'hint' mechanism > >> and whether it should be decided per mmap() request or at the > >> task level. > > > > I think the reasonable way for an application to claim it's 63-bit clean > > is to make allocations with (void *)-1 as hint address. > > I do like the simplicity of that. > > But I wouldn't be surprised if some (crappy) code out there already > passes an address of -1. Probably it won't break if it starts getting > high addresses, but who knows. To make an application break we need two thing: - it sets hint address to -1 by mistake; - it uses upper bit to encode its info; I would be surprise if such combination exists in real world. But let me know if you have any particular code in mind. > An alternative would be to only interpret the hint as requesting a large > address if it's >= 64TB && < TASK_SIZE_MAX. Nope. That doesn't work if you take into accounting further extension of the address space. Consider extension x86 to 6-level page tables. User-space has 63-bit address space. TASK_SIZE_MAX is bumped to (1UL << 63) - PAGE_SIZE. An application wants access to full address space. It gets recompiled using new TASK_SIZE_MAX as hint address. And everything works fine. But only on machine with 6-level paging enabled. If we run the same application binary on machine with older kernel and 5-level paging, the application will get access to only 47-bit address space, not 56-bit, as hint address is more than TASK_SIZE_MAX in this configuration. > If we're really worried about breaking userspace then a new MMAP flag > seems like the safest option? > > I don't feel particularly strongly about any option, but like I said my > main concern is that x86 & powerpc end up with the same behaviour. > > And whatever we end up with someone will need to do an update to the man > page for mmap. Sure. -- Kirill A. Shutemov
next prev parent reply other threads:[~2017-04-12 11:11 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-04-06 14:00 [PATCH 0/8] x86: 5-level paging enabling for v4.12, Part 4 Kirill A. Shutemov 2017-04-06 14:00 ` Kirill A. Shutemov 2017-04-06 14:00 ` [PATCH 1/8] x86/boot/64: Rewrite startup_64 in C Kirill A. Shutemov 2017-04-06 14:00 ` Kirill A. Shutemov 2017-04-06 14:01 ` [PATCH 2/8] x86/boot/64: Rename init_level4_pgt and early_level4_pgt Kirill A. Shutemov 2017-04-06 14:01 ` [PATCH 3/8] x86/boot/64: Add support of additional page table level during early boot Kirill A. Shutemov 2017-04-06 14:01 ` Kirill A. Shutemov 2017-04-11 7:02 ` Ingo Molnar 2017-04-11 7:02 ` Ingo Molnar 2017-04-11 10:51 ` Kirill A. Shutemov 2017-04-11 10:51 ` Kirill A. Shutemov 2017-04-11 11:28 ` Ingo Molnar 2017-04-11 11:28 ` Ingo Molnar 2017-04-11 11:46 ` Kirill A. Shutemov 2017-04-11 11:46 ` Kirill A. Shutemov 2017-04-11 14:09 ` Andi Kleen 2017-04-12 10:18 ` Kirill A. Shutemov 2017-04-17 10:32 ` Ingo Molnar 2017-04-17 10:32 ` Ingo Molnar 2017-04-18 8:59 ` Kirill A. Shutemov 2017-04-18 8:59 ` Kirill A. Shutemov 2017-04-18 10:15 ` Kirill A. Shutemov 2017-04-18 11:10 ` Kirill A. Shutemov 2017-04-18 11:10 ` Kirill A. Shutemov 2017-04-06 14:01 ` [PATCH 4/8] x86/mm: Add sync_global_pgds() for configuration with 5-level paging Kirill A. Shutemov 2017-04-06 14:01 ` Kirill A. Shutemov 2017-04-06 14:01 ` [PATCH 5/8] x86/mm: Make kernel_physical_mapping_init() support " Kirill A. Shutemov 2017-04-06 14:01 ` Kirill A. Shutemov 2017-04-06 14:01 ` [PATCH 6/8] x86/mm: Add support for 5-level paging for KASLR Kirill A. Shutemov 2017-04-06 14:01 ` Kirill A. Shutemov 2017-04-06 14:01 ` [PATCH 7/8] x86: Enable 5-level paging support Kirill A. Shutemov 2017-04-06 14:01 ` Kirill A. Shutemov 2017-04-06 14:52 ` Juergen Gross 2017-04-06 15:24 ` Kirill A. Shutemov 2017-04-06 15:56 ` Juergen Gross 2017-04-06 14:01 ` [PATCH 8/8] x86/mm: Allow to have userspace mappings above 47-bits Kirill A. Shutemov 2017-04-06 14:01 ` Kirill A. Shutemov 2017-04-06 18:43 ` Dmitry Safonov 2017-04-06 19:15 ` Dmitry Safonov 2017-04-06 23:21 ` Kirill A. Shutemov 2017-04-06 23:24 ` [PATCHv2 " Kirill A. Shutemov 2017-04-06 23:24 ` Kirill A. Shutemov 2017-04-07 11:32 ` Dmitry Safonov 2017-04-07 15:44 ` [PATCHv3 " Kirill A. Shutemov 2017-04-07 16:37 ` Dmitry Safonov 2017-04-13 11:30 ` [PATCHv4 0/9] x86: 5-level paging enabling for v4.12, Part 4 Kirill A. Shutemov 2017-04-13 11:30 ` Kirill A. Shutemov 2017-04-13 11:30 ` [PATCHv4 1/9] x86/asm: Fix comment in return_from_SYSCALL_64 Kirill A. Shutemov 2017-04-13 11:30 ` Kirill A. Shutemov 2017-04-13 11:30 ` [PATCHv4 2/9] x86/boot/64: Rewrite startup_64 in C Kirill A. Shutemov 2017-04-13 11:30 ` Kirill A. Shutemov 2017-04-13 11:30 ` [PATCHv4 3/9] x86/boot/64: Rename init_level4_pgt and early_level4_pgt Kirill A. Shutemov 2017-04-13 11:30 ` Kirill A. Shutemov 2017-04-13 11:30 ` [PATCHv4 4/9] x86/boot/64: Add support of additional page table level during early boot Kirill A. Shutemov 2017-04-13 11:30 ` Kirill A. Shutemov 2017-04-13 11:30 ` [PATCHv4 5/9] x86/mm: Add sync_global_pgds() for configuration with 5-level paging Kirill A. Shutemov 2017-04-13 11:30 ` Kirill A. Shutemov 2017-04-13 11:30 ` [PATCHv4 6/9] x86/mm: Make kernel_physical_mapping_init() support " Kirill A. Shutemov 2017-04-13 11:30 ` Kirill A. Shutemov 2017-04-13 11:30 ` [PATCHv4 7/9] x86/mm: Add support for 5-level paging for KASLR Kirill A. Shutemov 2017-04-13 11:30 ` Kirill A. Shutemov 2017-04-13 11:30 ` [PATCHv4 8/9] x86: Enable 5-level paging support Kirill A. Shutemov 2017-04-13 11:30 ` Kirill A. Shutemov 2017-04-13 11:30 ` [PATCHv4 9/9] x86/mm: Allow to have userspace mappings above 47-bits Kirill A. Shutemov 2017-04-13 11:30 ` Kirill A. Shutemov 2017-04-07 10:06 ` [PATCH 8/8] " Dmitry Safonov 2017-04-07 13:35 ` Anshuman Khandual 2017-04-07 13:35 ` Anshuman Khandual 2017-04-07 15:59 ` Kirill A. Shutemov 2017-04-07 15:59 ` Kirill A. Shutemov 2017-04-07 16:09 ` hpa 2017-04-07 16:09 ` hpa 2017-04-07 16:20 ` Kirill A. Shutemov 2017-04-12 10:41 ` Michael Ellerman 2017-04-12 11:11 ` Kirill A. Shutemov [this message] 2017-04-12 11:11 ` Kirill A. Shutemov
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