From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Kirill A. Shutemov" Subject: Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Date: Fri, 26 May 2017 18:58:12 +0300 Message-ID: <20170526155812.gdc6x6pz2howdpjb@node.shutemov.name> References: <20170525203334.867-1-kirill.shutemov@linux.intel.com> <20170526130057.t7zsynihkdtsepkf@node.shutemov.name> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: owner-linux-mm@kvack.org To: Linus Torvalds Cc: "Kirill A. Shutemov" , Andrew Morton , the arch/x86 maintainers , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andi Kleen , Dave Hansen , Andy Lutomirski , "linux-arch@vger.kernel.org" , linux-mm , Linux Kernel Mailing List List-Id: linux-arch.vger.kernel.org On Fri, May 26, 2017 at 08:51:48AM -0700, Linus Torvalds wrote: > On Fri, May 26, 2017 at 6:00 AM, Kirill A. Shutemov > wrote: > > > > I don't see how kernel threads can use 4-level paging. It doesn't work > > from virtual memory layout POV. Kernel claims half of full virtual address > > space for itself -- 256 PGD entries, not one as we would effectively have > > in case of switching to 4-level paging. For instance, addresses, where > > vmalloc and vmemmap are mapped, are not canonical with 4-level paging. > > I would have just assumed we'd map the kernel in the shared part that > fits in the top 47 bits. > > But it sounds like you can't switch back and forth anyway, so I guess it's moot. > > Where *is* the LA57 documentation, btw? I had an old x86 architecture > manual, so I updated it, but LA57 isn't mentioned in the new one > either. It's in a separate white paper for now: https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf -- Kirill A. Shutemov -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f66.google.com ([74.125.82.66]:33668 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754577AbdEZP6Q (ORCPT ); Fri, 26 May 2017 11:58:16 -0400 Received: by mail-wm0-f66.google.com with SMTP id b84so4748667wmh.0 for ; Fri, 26 May 2017 08:58:15 -0700 (PDT) Date: Fri, 26 May 2017 18:58:12 +0300 From: "Kirill A. Shutemov" Subject: Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Message-ID: <20170526155812.gdc6x6pz2howdpjb@node.shutemov.name> References: <20170525203334.867-1-kirill.shutemov@linux.intel.com> <20170526130057.t7zsynihkdtsepkf@node.shutemov.name> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-arch-owner@vger.kernel.org List-ID: To: Linus Torvalds Cc: "Kirill A. Shutemov" , Andrew Morton , the arch/x86 maintainers , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andi Kleen , Dave Hansen , Andy Lutomirski , "linux-arch@vger.kernel.org" , linux-mm , Linux Kernel Mailing List Message-ID: <20170526155812.JnStPVA8VF0IPHQ-CGA4gT9xst8dTkRWb-o53uJixKg@z> On Fri, May 26, 2017 at 08:51:48AM -0700, Linus Torvalds wrote: > On Fri, May 26, 2017 at 6:00 AM, Kirill A. Shutemov > wrote: > > > > I don't see how kernel threads can use 4-level paging. It doesn't work > > from virtual memory layout POV. Kernel claims half of full virtual address > > space for itself -- 256 PGD entries, not one as we would effectively have > > in case of switching to 4-level paging. For instance, addresses, where > > vmalloc and vmemmap are mapped, are not canonical with 4-level paging. > > I would have just assumed we'd map the kernel in the shared part that > fits in the top 47 bits. > > But it sounds like you can't switch back and forth anyway, so I guess it's moot. > > Where *is* the LA57 documentation, btw? I had an old x86 architecture > manual, so I updated it, but LA57 isn't mentioned in the new one > either. It's in a separate white paper for now: https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf -- Kirill A. Shutemov