From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ingo Molnar Subject: Re: [PATCHv7 13/14] x86: Enable 5-level paging support Date: Thu, 22 Jun 2017 11:24:54 +0200 Message-ID: <20170622092454.n4f2uho5lsp6ox4q@gmail.com> References: <20170606113133.22974-1-kirill.shutemov@linux.intel.com> <20170606113133.22974-14-kirill.shutemov@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20170606113133.22974-14-kirill.shutemov@linux.intel.com> Sender: owner-linux-mm@kvack.org To: "Kirill A. Shutemov" Cc: Linus Torvalds , Andrew Morton , x86@kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andi Kleen , Dave Hansen , Andy Lutomirski , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org List-Id: linux-arch.vger.kernel.org * Kirill A. Shutemov wrote: > Most of things are in place and we can enable support of 5-level paging. > > The patch makes XEN_PV dependent on !X86_5LEVEL. XEN_PV is not ready to > work with 5-level paging. Please make a short comment about that in the Kconfig code as well, instead of a silent, undocumented 'depends' clause. > config PGTABLE_LEVELS > int > + default 5 if X86_5LEVEL > default 4 if X86_64 > default 3 if X86_PAE > default 2 > @@ -1390,6 +1391,10 @@ config X86_PAE > has the cost of more pagetable lookup overhead, and also > consumes more pagetable space per process. > > +config X86_5LEVEL > + bool "Enable 5-level page tables support" > + depends on X86_64 So since users will be enabling it, this needs a proper help text that explains what hardware supports it ("future Intel CPUs" will do if models are not public yet), a short blurb about what it's good for - and a link to the Documentation/ file explaining it all. Thanks, Ingo -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-f196.google.com ([209.85.128.196]:36468 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752987AbdFVJY6 (ORCPT ); Thu, 22 Jun 2017 05:24:58 -0400 Date: Thu, 22 Jun 2017 11:24:54 +0200 From: Ingo Molnar Subject: Re: [PATCHv7 13/14] x86: Enable 5-level paging support Message-ID: <20170622092454.n4f2uho5lsp6ox4q@gmail.com> References: <20170606113133.22974-1-kirill.shutemov@linux.intel.com> <20170606113133.22974-14-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170606113133.22974-14-kirill.shutemov@linux.intel.com> Sender: linux-arch-owner@vger.kernel.org List-ID: To: "Kirill A. Shutemov" Cc: Linus Torvalds , Andrew Morton , x86@kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andi Kleen , Dave Hansen , Andy Lutomirski , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Message-ID: <20170622092454.mdraGMOImZmpCR4pjOcqtMLAWLCoUN2ms6GoSHfAsR4@z> * Kirill A. Shutemov wrote: > Most of things are in place and we can enable support of 5-level paging. > > The patch makes XEN_PV dependent on !X86_5LEVEL. XEN_PV is not ready to > work with 5-level paging. Please make a short comment about that in the Kconfig code as well, instead of a silent, undocumented 'depends' clause. > config PGTABLE_LEVELS > int > + default 5 if X86_5LEVEL > default 4 if X86_64 > default 3 if X86_PAE > default 2 > @@ -1390,6 +1391,10 @@ config X86_PAE > has the cost of more pagetable lookup overhead, and also > consumes more pagetable space per process. > > +config X86_5LEVEL > + bool "Enable 5-level page tables support" > + depends on X86_64 So since users will be enabling it, this needs a proper help text that explains what hardware supports it ("future Intel CPUs" will do if models are not public yet), a short blurb about what it's good for - and a link to the Documentation/ file explaining it all. Thanks, Ingo