From: "Jonathan Neuschäfer" <j.neuschaefer@gmx.net>
To: patches@groups.riscv.org
Cc: peterz@infradead.org, mingo@redhat.com, mcgrof@kernel.org,
viro@zeniv.linux.org.uk, sfr@canb.auug.org.au,
nicolas.dichtel@6wind.com, rmk+kernel@armlinux.org.uk,
msalter@redhat.com, tklauser@distanz.ch, will.deacon@arm.com,
james.hogan@imgtec.com, paul.gortmaker@windriver.com,
linux@roeck-us.net, linux-kernel@vger.kernel.org,
linux-arch@vger.kernel.org, albert@sifive.com,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [patches] [PATCH 1/9] RISC-V: Init and Halt Code
Date: Tue, 4 Jul 2017 23:54:01 +0200 [thread overview]
Message-ID: <20170704215401.whmxuedbu3jd7uf5@latitude> (raw)
In-Reply-To: <20170704195102.3974-2-palmer@dabbelt.com>
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Hi, below are some small comments.
On Tue, Jul 04, 2017 at 12:50:54PM -0700, Palmer Dabbelt wrote:
> This contains the various __init C functions, the initial assembly
> kernel entry point, and the code to reset the system. When a file was
> init-related, it contains
It contains what?
> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
[...]
> +#ifdef CONFIG_GENERIC_BUG
> +#define __BUG_INSN _AC(0x00100073, UL) /* sbreak */
This should be ebreak, not sbreak, in Priv Spec 1.10, AFAICT.
I guess binutils still understands sbreak, but it's nicer to stick to
the spec, IMHO.
> +#define BUG() \
> +do { \
> + __asm__ __volatile__ ( \
> + "1:\n\t" \
> + "sbreak\n" \
ebreak
> + ".pushsection __bug_table,\"a\"\n\t" \
> + "2:\n\t" \
> + __BUG_ENTRY "\n\t" \
> + ".org 2b + %2\n\t" \
> + ".popsection" \
> + : \
> + : "i" (__FILE__), "i" (__LINE__), \
> + "i" (sizeof(struct bug_entry))); \
> + unreachable(); \
> +} while (0)
> +#endif /* !__ASSEMBLY__ */
> +#else /* CONFIG_GENERIC_BUG */
> +#ifndef __ASSEMBLY__
> +#define BUG() \
> +do { \
> + __asm__ __volatile__ ("sbreak\n"); \
ebreak
> + unreachable(); \
> +} while (0)
> +#endif /* !__ASSEMBLY__ */
> +#endif /* CONFIG_GENERIC_BUG */
[...]
> +#define DO_ERROR_INFO(name, signo, code, str) \
> +asmlinkage void name(struct pt_regs *regs) \
> +{ \
> + do_trap_error(regs, signo, code, regs->sepc, "Oops - " str); \
> +}
> +
> +DO_ERROR_INFO(do_trap_unknown,
> + SIGILL, ILL_ILLTRP, "unknown exception");
> +DO_ERROR_INFO(do_trap_insn_misaligned,
> + SIGBUS, BUS_ADRALN, "instruction address misaligned");
> +DO_ERROR_INFO(do_trap_insn_fault,
> + SIGBUS, BUS_ADRALN, "instruction access fault");
For a general instruction access fault, BUS_ADRALN seems wrong. A
variant of SIGSEGV seems more appropriate, IMHO.
Jonathan Neuschäfer
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next prev parent reply other threads:[~2017-07-04 21:54 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-04 19:50 RISC-V Linux Port v4 Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 1/9] RISC-V: Init and Halt Code Palmer Dabbelt
2017-07-04 19:50 ` Palmer Dabbelt
2017-07-04 19:50 ` Palmer Dabbelt
[not found] ` <alpine.DEB.2.20.1707042224560.2131@nanos>
2017-07-04 21:17 ` [patches] " Karsten Merker
2017-07-05 6:39 ` Thomas Gleixner
2017-07-04 21:54 ` Jonathan Neuschäfer [this message]
2017-07-04 21:54 ` [patches] " Jonathan Neuschäfer
2017-07-06 22:34 ` Palmer Dabbelt
2017-07-07 12:58 ` Jonathan Neuschäfer
2017-07-10 20:39 ` Palmer Dabbelt
2017-07-10 20:39 ` Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 2/9] RISC-V: Atomic and Locking Code Palmer Dabbelt
2017-07-04 19:50 ` Palmer Dabbelt
2017-07-04 19:50 ` Palmer Dabbelt
2017-07-05 8:43 ` Peter Zijlstra
2017-07-06 11:08 ` Boqun Feng
2017-07-06 7:26 ` Peter Zijlstra
2017-07-07 1:04 ` Palmer Dabbelt
2017-07-07 2:14 ` Boqun Feng
2017-07-10 20:39 ` Palmer Dabbelt
2017-07-10 20:39 ` Palmer Dabbelt
2017-07-07 8:08 ` Peter Zijlstra
2017-07-07 8:08 ` Peter Zijlstra
2017-07-10 20:39 ` Palmer Dabbelt
2017-07-10 20:39 ` Palmer Dabbelt
2017-07-06 10:33 ` Boqun Feng
2017-07-06 10:33 ` Boqun Feng
2017-07-07 13:16 ` [patches] " Jonathan Neuschäfer
2017-07-10 20:39 ` Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 3/9] RISC-V: Generic library routines and assembly Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 4/9] RISC-V: ELF and module implementation Palmer Dabbelt
2017-07-04 19:50 ` Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 5/9] RISC-V: Task implementation Palmer Dabbelt
2017-07-04 19:50 ` Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt
2017-07-04 19:51 ` [PATCH 7/9] RISC-V: Paging and MMU Palmer Dabbelt
2017-07-04 19:51 ` Palmer Dabbelt
2017-07-04 19:51 ` Palmer Dabbelt
2017-07-04 19:51 ` [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt
2017-07-04 19:51 ` Palmer Dabbelt
2017-07-05 10:24 ` James Hogan
2017-07-06 2:01 ` Christoph Hellwig
2017-07-06 8:55 ` Will Deacon
2017-07-06 15:34 ` Christoph Hellwig
2017-07-06 15:34 ` Christoph Hellwig
2017-07-06 15:45 ` Will Deacon
2017-07-06 15:45 ` Will Deacon
[not found] ` <mhng-f92ef7c4-049a-4a71-be12-c600d1d7858b@palmer-si-x1c4>
2017-07-10 20:18 ` Palmer Dabbelt
2017-07-11 13:22 ` Will Deacon
2017-07-11 13:55 ` Christoph Hellwig
2017-07-11 17:28 ` Palmer Dabbelt
2017-07-11 17:28 ` Palmer Dabbelt
2017-07-11 17:07 ` Palmer Dabbelt
2017-07-06 15:34 ` Dave P Martin
2017-07-04 19:51 ` [PATCH 9/9] RISC-V: Build Infastructure Palmer Dabbelt
2017-07-04 19:51 ` Palmer Dabbelt
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