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From: James Hogan <james.hogan@imgtec.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: peterz@infradead.org, mingo@redhat.com, mcgrof@kernel.org,
	viro@zeniv.linux.org.uk, sfr@canb.auug.org.au,
	nicolas.dichtel@6wind.com, rmk+kernel@armlinux.org.uk,
	msalter@redhat.com, tklauser@distanz.ch, will.deacon@arm.com,
	paul.gortmaker@windriver.com, linux@roeck-us.net,
	linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	albert@sifive.com, patches@groups.riscv.org
Subject: Re: [PATCH 8/9] RISC-V: User-facing API
Date: Wed, 5 Jul 2017 11:24:33 +0100	[thread overview]
Message-ID: <20170705102433.GC6973@jhogan-linux.le.imgtec.org> (raw)
In-Reply-To: <20170704195102.3974-9-palmer@dabbelt.com>

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On Tue, Jul 04, 2017 at 12:51:01PM -0700, Palmer Dabbelt wrote:
> diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
> new file mode 100644
> index 000000000000..2720d5e97354
> --- /dev/null
> +++ b/arch/riscv/kernel/ptrace.c
> @@ -0,0 +1,138 @@

> +/* Put registers back to task. */
> +static void putregs(struct task_struct *child, struct pt_regs *uregs)
> +{
> +	struct pt_regs *regs = task_pt_regs(child);
> +	*regs = *uregs;
> +}
> +
> +static int riscv_gpr_get(struct task_struct *target,
> +			 const struct user_regset *regset,
> +			 unsigned int pos, unsigned int count,
> +			 void *kbuf, void __user *ubuf)
> +{
> +	struct pt_regs *regs;
> +
> +	regs = task_pt_regs(target);
> +	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, regs, 0,
> +				   sizeof(*regs));

sizeof(struct pt_regs) > sizeof(struct user_regs_struct), which allows
supervisor registers to be copied too. I think you should be using
sizeof(struct user_regs_struct) instead.

> +}
> +
> +static int riscv_gpr_set(struct task_struct *target,
> +			 const struct user_regset *regset,
> +			 unsigned int pos, unsigned int count,
> +			 const void *kbuf, const void __user *ubuf)
> +{
> +	int ret;
> +	struct pt_regs regs;
> +
> +	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &regs, 0,
> +				 sizeof(regs));

same

> +	if (ret)
> +		return ret;
> +
> +	putregs(target, &regs);

you're still copying via the stack without initialising the non-written
fields. If userland does a short PTRACE_SETREGSET the remaining fields
will be copied from the uninitialised kernel stack and accessible to
userland via PTRACE_GETREGSET.

Even if the user does a full sizeof(struct user_regs_struct) (not
pt_regs) PTRACE_SETREGSET the supervisor registers will be overwritten
with uninitialised stack content.

> diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
> new file mode 100644
> index 000000000000..4419604ff46c
> --- /dev/null
> +++ b/arch/riscv/kernel/sys_riscv.c

> +SYSCALL_DEFINE3(sysriscv_cmpxchg32, u32 __user *, ptr, u32, new, u32, old)
> +{
> +	u32 prev;
> +	unsigned int err;
> +
> +	if (!access_ok(VERIFY_WRITE, ptr, sizeof(*ptr)))
> +		return -EFAULT;
> +
> +#ifdef CONFIG_ISA_A
> +	err = 0;
> +	prev = cmpxchg32(ptr, old, new);

I think this needs a special version of cmpxchg (or for cmpxchg to be
modified) with fixup protection to return -EFAULT in case the page isn't
mapped or is paged out/read only.

> +#else
> +	preempt_disable();
> +	err = __get_user(prev, ptr);
> +	if (likely(!err && prev == old))
> +		err = __put_user(new, ptr);
> +	preempt_enable();
> +#endif
> +
> +	return unlikely(err) ? err : prev;
> +}
> +
> +SYSCALL_DEFINE3(sysriscv_cmpxchg64, u64 __user *, ptr, u64, new, u64, old)
> +{
> +#ifdef CONFIG_64BIT
> +	u64 prev;
> +	unsigned int err;
> +
> +	if (!access_ok(VERIFY_WRITE, ptr, sizeof(*ptr)))
> +		return -EFAULT;
> +
> +#ifdef CONFIG_ISA_A
> +	err = 0;
> +	prev = cmpxchg64(ptr, old, new);

Likewise

> +#else
> +	preempt_disable();
> +	err = __get_user(prev, ptr);
> +	if (likely(!err && prev == old))
> +		err = __put_user(new, ptr);
> +	preempt_enable();
> +#endif
> +	return unlikely(err) ? err : prev;
> +#else
> +	return -ENOTSUPP;

I think -ENOSYS is more standard for missing/unimplemented system calls.

A better way IMO would be to #ifdef the definitions in unistd.h, then
the __NR_* definitions could also be more accurately extracted from the
kernel headers, and you could just ifdef CONFIG_64BIT the whole syscall
implementation, i.e.:

> diff --git a/arch/riscv/include/uapi/asm/unistd.h b/arch/riscv/include/uapi/asm/unistd.h
> new file mode 100644
> index 000000000000..37a5429cc896
> --- /dev/null
> +++ b/arch/riscv/include/uapi/asm/unistd.h
> @@ -0,0 +1,23 @@

> +/*
> + * These system calls add support for AMOs on RISC-V systems without support
> + * for the A extension.
> + */
> +#define __NR_sysriscv_cmpxchg32		(__NR_arch_specific_syscall + 0)
> +__SYSCALL(__NR_sysriscv_cmpxchg32, sys_sysriscv_cmpxchg32)

+ifdef WHATEVER_BUILTIN_GCC_DEFINES_FOR_64BIT_RISCV_ABI

In case its helpful the following should list builtin preprocessor
defines for given CFLAGS:
${CROSS_COMPILE}gcc ${CFLAGS} -dM -E -</dev/null

> +#define __NR_sysriscv_cmpxchg64		(__NR_arch_specific_syscall + 1)
> +__SYSCALL(__NR_sysriscv_cmpxchg64, sys_sysriscv_cmpxchg64)

+endif

Cheers
James

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  reply	other threads:[~2017-07-05 10:24 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-04 19:50 RISC-V Linux Port v4 Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 1/9] RISC-V: Init and Halt Code Palmer Dabbelt
2017-07-04 19:50 ` Palmer Dabbelt
2017-07-04 19:50   ` Palmer Dabbelt
     [not found]   ` <alpine.DEB.2.20.1707042224560.2131@nanos>
2017-07-04 21:17     ` [patches] " Karsten Merker
2017-07-05  6:39       ` Thomas Gleixner
2017-07-04 21:54   ` [patches] " Jonathan Neuschäfer
2017-07-04 21:54     ` Jonathan Neuschäfer
2017-07-06 22:34     ` Palmer Dabbelt
2017-07-07 12:58       ` Jonathan Neuschäfer
2017-07-10 20:39         ` Palmer Dabbelt
2017-07-10 20:39           ` Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 2/9] RISC-V: Atomic and Locking Code Palmer Dabbelt
2017-07-04 19:50   ` Palmer Dabbelt
2017-07-05  8:43   ` Peter Zijlstra
2017-07-06 11:08     ` Boqun Feng
2017-07-06  7:26       ` Peter Zijlstra
2017-07-07  1:04     ` Palmer Dabbelt
2017-07-07  2:14       ` Boqun Feng
2017-07-10 20:39         ` Palmer Dabbelt
2017-07-10 20:39           ` Palmer Dabbelt
2017-07-07  8:08       ` Peter Zijlstra
2017-07-07  8:08         ` Peter Zijlstra
2017-07-10 20:39         ` Palmer Dabbelt
2017-07-10 20:39           ` Palmer Dabbelt
2017-07-06 10:33   ` Boqun Feng
2017-07-06 10:33     ` Boqun Feng
2017-07-07 13:16   ` [patches] " Jonathan Neuschäfer
2017-07-10 20:39     ` Palmer Dabbelt
2017-07-04 19:50 ` Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 3/9] RISC-V: Generic library routines and assembly Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 4/9] RISC-V: ELF and module implementation Palmer Dabbelt
2017-07-04 19:50   ` Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 5/9] RISC-V: Task implementation Palmer Dabbelt
2017-07-04 19:50 ` Palmer Dabbelt
2017-07-04 19:50 ` [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt
2017-07-04 19:51 ` [PATCH 7/9] RISC-V: Paging and MMU Palmer Dabbelt
2017-07-04 19:51   ` Palmer Dabbelt
2017-07-04 19:51 ` Palmer Dabbelt
2017-07-04 19:51 ` [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt
2017-07-05 10:24   ` James Hogan [this message]
2017-07-06  2:01   ` Christoph Hellwig
2017-07-06  8:55     ` Will Deacon
2017-07-06 15:34       ` Christoph Hellwig
2017-07-06 15:34         ` Christoph Hellwig
2017-07-06 15:45         ` Will Deacon
2017-07-06 15:45           ` Will Deacon
     [not found]           ` <mhng-f92ef7c4-049a-4a71-be12-c600d1d7858b@palmer-si-x1c4>
2017-07-10 20:18             ` Palmer Dabbelt
2017-07-11 13:22             ` Will Deacon
2017-07-11 13:55               ` Christoph Hellwig
2017-07-11 17:28                 ` Palmer Dabbelt
2017-07-11 17:28                   ` Palmer Dabbelt
2017-07-11 17:07               ` Palmer Dabbelt
2017-07-06 15:34   ` Dave P Martin
2017-07-04 19:51 ` Palmer Dabbelt
2017-07-04 19:51 ` [PATCH 9/9] RISC-V: Build Infastructure Palmer Dabbelt
2017-07-04 19:51   ` Palmer Dabbelt
  -- strict thread matches above, loose matches on Subject: below --
2017-06-06 22:59 RISC-V Linux Port v2 Palmer Dabbelt
2017-06-28 18:55 ` RISC-V Linux Port v3 Palmer Dabbelt
2017-06-28 18:55   ` [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt
2017-06-28 21:49     ` Thomas Gleixner
2017-06-28 21:52       ` Thomas Gleixner
2017-06-29 17:22       ` Palmer Dabbelt
2017-06-28 22:42     ` James Hogan
2017-06-29 21:42       ` Palmer Dabbelt
2017-07-03 23:06         ` James Hogan
2017-07-05 16:49           ` Palmer Dabbelt

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