From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: Re: [PATCH] ia64: fix barrier placement for write* / dma mapping Date: Wed, 1 Aug 2018 09:29:47 +0200 Message-ID: <20180801072947.GD20224@lst.de> References: <20180731172031.4447-1-hch@lst.de> <20180731172031.4447-2-hch@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: okaya@codeaurora.org Cc: Christoph Hellwig , Tony Luck , Fenghua Yu , Arnd Bergmann , linux-ia64@vger.kernel.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, okaya@kernel.org List-Id: linux-arch.vger.kernel.org On Tue, Jul 31, 2018 at 11:41:23PM -0700, okaya@codeaurora.org wrote: > I asked this question to Tony Luck before. If I remember right, > his answer was: > > CPU guarantees outstanding writes to be flushed when a register write > instruction is executed and an additional barrier instruction is not > needed. That would be great. It still doesn't explain the barriers in the dma sync routines. Those have been there since the following commit in the history tree: commit 66b99421d118a5ddd98a72913670b0fcf0a38d45 Author: Andrew Morton Date: Sat Mar 13 17:05:37 2004 -0800 [PATCH] DMA: Fill gaping hole in DMA API interfaces. From: "David S. Miller" which in fact only added them for the HP zx1 platform, and doesn't contain any good explanation of why we need a barrier. So I guess the right answer might be to just remove these barriers without replacement. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from verein.lst.de ([213.95.11.211]:32929 "EHLO newverein.lst.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732300AbeHAJJf (ORCPT ); Wed, 1 Aug 2018 05:09:35 -0400 Date: Wed, 1 Aug 2018 09:29:47 +0200 From: Christoph Hellwig Subject: Re: [PATCH] ia64: fix barrier placement for write* / dma mapping Message-ID: <20180801072947.GD20224@lst.de> References: <20180731172031.4447-1-hch@lst.de> <20180731172031.4447-2-hch@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-arch-owner@vger.kernel.org List-ID: To: okaya@codeaurora.org Cc: Christoph Hellwig , Tony Luck , Fenghua Yu , Arnd Bergmann , linux-ia64@vger.kernel.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, okaya@kernel.org Message-ID: <20180801072947.SHVRKLfiiltSaK1vT83GsjslpFalitUQ4oKQ21gzeEw@z> On Tue, Jul 31, 2018 at 11:41:23PM -0700, okaya@codeaurora.org wrote: > I asked this question to Tony Luck before. If I remember right, > his answer was: > > CPU guarantees outstanding writes to be flushed when a register write > instruction is executed and an additional barrier instruction is not > needed. That would be great. It still doesn't explain the barriers in the dma sync routines. Those have been there since the following commit in the history tree: commit 66b99421d118a5ddd98a72913670b0fcf0a38d45 Author: Andrew Morton Date: Sat Mar 13 17:05:37 2004 -0800 [PATCH] DMA: Fill gaping hole in DMA API interfaces. From: "David S. Miller" which in fact only added them for the HP zx1 platform, and doesn't contain any good explanation of why we need a barrier. So I guess the right answer might be to just remove these barriers without replacement.