From mboxrd@z Thu Jan 1 00:00:00 1970 From: Guo Ren Subject: Re: [PATCH V3 22/26] dt-bindings: interrupt-controller: C-SKY SMP intc Date: Fri, 7 Sep 2018 14:07:30 +0800 Message-ID: <20180907060730.GB16834@guoren> References: <20180906022322.GA30251@guoren-Inspiron-7460> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Arnd Bergmann Cc: Rob Herring , linux-arch , Linux Kernel Mailing List , Thomas Gleixner , Daniel Lezcano , Jason Cooper , c-sky_gcc_upstream@c-sky.com, gnu-csky@mentor.com, Thomas Petazzoni , wbx@uclibc-ng.org, Greentime Hu List-Id: linux-arch.vger.kernel.org On Thu, Sep 06, 2018 at 03:03:16PM +0200, Arnd Bergmann wrote: > > INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE); > > It that reliable? I remember a similar situation with some registers on ARM > that are usually identified through a special CPU register, but in some > cases the SoC integrator put the wrong address in there, so we need to > look up the address in DT anyway. Yes, it's reliable. This interrupt is combined with CPU and not on AXI or APB. Soc just give a hole in the address space and tell the CPU where the address is with 20 wire-signals. Guo Ren From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:34303 "EHLO smtp2200-217.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725933AbeIGKrB (ORCPT ); Fri, 7 Sep 2018 06:47:01 -0400 Date: Fri, 7 Sep 2018 14:07:30 +0800 From: Guo Ren Subject: Re: [PATCH V3 22/26] dt-bindings: interrupt-controller: C-SKY SMP intc Message-ID: <20180907060730.GB16834@guoren> References: <20180906022322.GA30251@guoren-Inspiron-7460> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-arch-owner@vger.kernel.org List-ID: To: Arnd Bergmann Cc: Rob Herring , linux-arch , Linux Kernel Mailing List , Thomas Gleixner , Daniel Lezcano , Jason Cooper , c-sky_gcc_upstream@c-sky.com, gnu-csky@mentor.com, Thomas Petazzoni , wbx@uclibc-ng.org, Greentime Hu Message-ID: <20180907060730.QnbmIEhSlhr9O5-cs0Yk9zpXIF95SSwxlA43ggDO9a0@z> On Thu, Sep 06, 2018 at 03:03:16PM +0200, Arnd Bergmann wrote: > > INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE); > > It that reliable? I remember a similar situation with some registers on ARM > that are usually identified through a special CPU register, but in some > cases the SoC integrator put the wrong address in there, so we need to > look up the address in DT anyway. Yes, it's reliable. This interrupt is combined with CPU and not on AXI or APB. Soc just give a hole in the address space and tell the CPU where the address is with 20 wire-signals. Guo Ren